HBM SoC Physical Design Engineer Intern

Micron Technology, Inc; Folsom (CA); On-site; USD 81,000 - 104,000; Full time

Job summary

Micron Technology, Inc is seeking a motivated SoC Physical Design Intern to support the HBM team in implementing advanced memory designs for AI and data center workloads.

You will gain hands-on experience with floorplanning, timing analysis, signoff flows, and automation using Python and Tcl, collaborating across architecture, RTL, verification, and signoff to deliver high‑performance, power‑efficient silicon.

Qualifications

• Pursuing a Master's in Electrical/Computer Engineering or related field.
• Knowledge of ASIC design flow: synthesis, place-and-route, STA, physical verification.
• Programming/scripting in Python, Tcl, Perl, or Shell.

Responsibilities

• Support physical implementation: floorplanning, placement, clock tree synthesis, routing, and optimization.
• Analyze timing, power, area, congestion and physical verification results for improvements.
• Assist with STA, timing closure, and debugging across modes and corners.
• Develop automation tools, scripts, reports, and workflows using Python, Tcl, Shell, and AI-assisted solutions.

Skills

ASIC design flow

VLSI

Python

Tcl

Shell scripting

Timing analysis

Teamwork

AI/LLM familiarity

Education

Master's degree in Electrical Engineering / Computer Engineering

Tools

Cadence Innovus/Tempus

Synopsys ICC2/PrimeTime

Siemens Calibre

Job description

Micron Technology, Inc is seeking a motivated SoC Physical Design Intern to support the HBM team in implementing advanced memory designs for AI and data center workloads.

You will gain hands-on experience with floorplanning, timing analysis, signoff flows, and automation using Python and Tcl, collaborating across architecture, RTL, verification, and signoff to deliver high‑performance, power‑efficient silicon.