Lead HBM SoC Physical Design Engineer

Micron Technology, Inc.; Richardson (TX); On-site; USD 130,000 - 210,000; Full time

Benefits offered by this job

Medical, dental, vision plans

Paid time off & holidays

401(k) or equivalent retirement plan

Job summary

Micron Technology, Inc. is seeking a hands‑on SoC Physical Design Engineer within the Heterogeneous Integration Group to drive implementation from netlist to GDSII. You will collaborate across RTL, DFT, IP, packaging and manufacturing to ensure best-in-class PPA and robust signoff for tape-out.

The role emphasizes floor-planning, placement, CTS, routing, timing/power integrity, and post‑silicon debug. A strong background in advanced-node PD and DFT coordination is required.

Qualifications

• Proven experience in SoC physical design from netlist to GDSII on advanced nodes.
• Strong understanding of timing closure, SDC constraints and physical verification.
• Experience with UPF/CPF power intent and power delivery considerations.

Responsibilities

• Own physical implementation for SoC blocks/top-level including floorplanning, placement, CTS, routing and optimization to meet PPA targets.
• Drive timing closure across MMMC scenarios in collaboration with RTL/architecture/STA teams.
• Coordinate DRC/LVS/ERD signoff and mbist/DFT integration with packaging and manufacturing.
• Support tape-out execution, ECO flows and post-silicon debug correlation.

Skills

SoC design

Timing closure

Automation scripting

Education

BSc/MSc in Electrical/Computer Engineering

Tools

Cadence Innovus

Cadence Tempus

Siemens Calibre

Power integrity tools

Job description

Micron Technology, Inc. is seeking a hands‑on SoC Physical Design Engineer within the Heterogeneous Integration Group to drive implementation from netlist to GDSII. You will collaborate across RTL, DFT, IP, packaging and manufacturing to ensure best-in-class PPA and robust signoff for tape-out.

The role emphasizes floor-planning, placement, CTS, routing, timing/power integrity, and post‑silicon debug. A strong background in advanced-node PD and DFT coordination is required.