HBM SoC Physical Design Engineer — Netlist to Tape-Out

Micron Technology; Folsom (CA); On-site; USD 121,000 - 205,000; Full time

Job summary

Micron Technology in Folsom, CA is seeking an experienced SoC Physical Design Engineer to drive implementation of advanced memory-centric designs from netlist to GDSII. You will collaborate with RTL, DFT, IP, packaging and manufacturing to deliver strong PPA and robust tape-out signoff across multiple generations.

This hands-on role emphasizes timing closure, power integrity and flow automation using industry tools, with opportunities to own blocks or top-level integration.

Qualifications

• Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes.
• Proficiency with EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, and Calibre.
• Solid understanding of STA, constraints, and closure techniques.
• Experience with power intent and power delivery concepts.
• Familiarity with DRC/LVS, parasitic extraction, and signoff processes.

Responsibilities

• Own physical implementation for SoC blocks/top-level, including floor-planning, placement, CTS, routing, and optimization to meet PPA targets.
• Drive timing closure across MMMC scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
• Integrate and implement IP with focus on robust physical integration and timing/power integrity.
• Coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff.
• Partner with DFT teams to ensure scan/MBIST requirements are feasible without compromising PPA or schedule.
• Collaborate with packaging, assembly, test, probe, and manufacturing to ensure manufacturability and quality.
• Support tape-out execution and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.

Skills

SoC Physical Design

EDA Tools

STA & Constraints

Power Integrity

Signoff & DRC/LVS

Education

Bachelors/Masters in Electrical or Computer Engineering

Tools

Cadence Innovus/Tempus

Synopsys ICC2/PrimeTime

Siemens Calibre

Job description

Micron Technology in Folsom, CA is seeking an experienced SoC Physical Design Engineer to drive implementation of advanced memory-centric designs from netlist to GDSII. You will collaborate with RTL, DFT, IP, packaging and manufacturing to deliver strong PPA and robust tape-out signoff across multiple generations.

This hands-on role emphasizes timing closure, power integrity and flow automation using industry tools, with opportunities to own blocks or top-level integration.