Senior SoC Physical Design Engineer: Lead Tapeout & PPA

Micron Technology; Folsom (CA); On-site; USD 177,000 - 334,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Paid time-off

Job summary

Micron Technology in Folsom, California is seeking a SoC Physical Design Engineer to drive advanced HBM SoC implementations from netlist to GDSII. You will collaborate closely with various teams to ensure optimal physical design and successful tapeout execution.

The ideal candidate has strong experience in SoC physical design, proficiency with EDA tools like Cadence Innovus, and excellent scripting skills. A degree in Electrical Engineering and a proven tapeout history are preferred.

Qualifications

• Strong experience in SoC physical design implementation from netlist to GDSII.
• Proficiency with industry EDA tools.
• Experience with power intent and delivery considerations.

Responsibilities

• Own physical implementation for SoC blocks and/or top-level.
• Drive timing closure across design scenarios.
• Collaborate with integration teams.

Skills

SoC physical design implementation

EDA tools proficiency

Scripting/automation skills

Power intent and delivery

Education

Bachelor’s or Master’s degree in Electrical Engineering or related field

Tools

Cadence Innovus

Synopsys ICC2

Siemens Calibre

Job description

Micron Technology in Folsom, California is seeking a SoC Physical Design Engineer to drive advanced HBM SoC implementations from netlist to GDSII. You will collaborate closely with various teams to ensure optimal physical design and successful tapeout execution.

The ideal candidate has strong experience in SoC physical design, proficiency with EDA tools like Cadence Innovus, and excellent scripting skills. A degree in Electrical Engineering and a proven tapeout history are preferred.