Senior SoC PD Lead – HBM & Integration

1000 Micron Technology, Inc.; Folsom (CA); On-site; USD 177,000 - 309,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Robust paid time-off program

Paid holidays

Flexible benefits

Job summary

Micron Technology, Inc. in the United States is seeking an SoC Physical Design Senior Manager, HBM, within the Heterogeneous Integration Group to lead a team responsible for the implementation of advanced HBM base-die designs from netlist to GDSII.

You will drive PPA targets and collaborate with RTL, IP, packaging and manufacturing to ensure robust signoff and successful tapeout. You will mentor engineers, plan resourcing, optimize flows, and leverage AI-driven workflows to accelerate design

Qualifications

• Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes.
• Proficiency with industry EDA tools (Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
• Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques.
• Experience with power intent and power delivery considerations (UPF/CPF concepts, power grid planning).
• Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, signoff handoff quality.
• Exposure to hierarchical physical design, top-level assembly, and large-scale integration methodology.
• Knowledge of IR/EM analysis, noise, coupling/crosstalk and mitigation strategies.
• Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full-cycle SoC development flows.
• Ability to work in a global, cross-functional environment with strong communication and debugging skills.
• Experience implementing AI flows and using agentic AI and LLMs.

Responsibilities

• Recruit, develop, and mentor a team of physical design engineers delivering HBM base die products.
• Plan project resourcing requirements and timelines.
• Prioritize resources across projects and individual assignments to meet aggressive product delivery schedules.
• Drive physical implementation for SoC blocks and/or top-level including floorplanning, placement, CTS, routing, and physical optimization to meet PPA targets.
• Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
• Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements.
• Integrate and implement complex IP with focus on robust physical integration and timing/power integrity.
• Perform and/or coordinate physical signoff including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
• Support tapeout execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
• Drive agentic AI development initiatives and develop AI/LLM driven workflows.

Skills

SoC physical design implementation

EDA tools proficiency

STA fundamentals

Power delivery concepts

Physical signoff knowledge

Hierarchical design experience

AI/LLM workflow familiarity

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree preferred

Tools

Cadence Innovus/Tempus

Synopsys ICC2/PrimeTime

Siemens Calibre

Job description

Micron Technology, Inc. in the United States is seeking an SoC Physical Design Senior Manager, HBM, within the Heterogeneous Integration Group to lead a team responsible for the implementation of advanced HBM base-die designs from netlist to GDSII.

You will drive PPA targets and collaborate with RTL, IP, packaging and manufacturing to ensure robust signoff and successful tapeout. You will mentor engineers, plan resourcing, optimize flows, and leverage AI-driven workflows to accelerate design