Senior SoC Physical Design Engineer: Tapeout & PPA

Micron Technology, Inc.; Folsom (CA); On-site; USD 177,000 - 334,000; Full time

Job summary

Micron Technology, Inc. is seeking an SoC Physical Design Engineer within the Heterogeneous Integration Group (HIG).

You will drive implementation of advanced SoC logic/base die from netlist to GDSII, collaborating with RTL, verification, DFT, IP providers, packaging and manufacturing to deliver PPA and robust tapeout signoff. Key responsibilities include floorplanning, placement, routing, timing closure across MMMC scenarios, and integration of complex IP with robust power integrity.

Qualifications

• Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes.
• Proficiency with EDA tools: Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre.
• Knowledge of UPF/CPF power delivery concepts and power integrity considerations.
• Exposure to hierarchical physical design and top-level assembly for large-scale integration.
• Proven tapeout history on advanced foundries (e.g., TSMC).
• Strong scripting abilities in Python, TCL, Perl, or shell.

Responsibilities

• Own physical implementation for SoC blocks and/or top-level, including floorplanning, placement, CTS, routing, and optimization to meet PPA targets.
• Drive timing closure across MMMC scenarios; collaborate with RTL, architecture, and STA for convergence.
• Ensure clocking/reset strategy, power architecture, and SoC integration meet requirements.
• Integrate complex IP (controllers, NOC, interfaces, MBIST/DFT) with robust physical integration and timing/power integrity.
• Coordinate physical signoff (DRC/LVS, EM/IR drop, timing), addressing violations efficiently.
• Collaborate with packaging, test, and manufacturing to ensure manufacturability and quality; support tapeout checks and post-silicon debug.
• Identify flow gaps and improve productivity via scripting/automation.

Skills

SoC physical design

Power integrity

Floorplanning & routing

Timing closure

IP integration

Scripting (Python/TCL/Perl)

Tapeout experience

Top-level integration

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field

Tools

Cadence Innovus/Tempus

Synopsys ICC2/PrimeTime

Siemens Calibre

Job description

Micron Technology, Inc. is seeking an SoC Physical Design Engineer within the Heterogeneous Integration Group (HIG).

You will drive implementation of advanced SoC logic/base die from netlist to GDSII, collaborating with RTL, verification, DFT, IP providers, packaging and manufacturing to deliver PPA and robust tapeout signoff. Key responsibilities include floorplanning, placement, routing, timing closure across MMMC scenarios, and integration of complex IP with robust power integrity.