HBM SoC Physical Design Engineer Intern

1000 Micron Technology, Inc.; Folsom (CA); On-site; USD 54,000 - 69,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. is seeking a SoC Physical Design Intern on the HBM team in the United States.

You will support the implementation of advanced HBM SoC designs and gain hands-on experience in physical design methodologies, timing analysis, signoff flows, and automation. You will work with veterans across architecture, RTL, verification, DFT, and signoff, contributing to next-generation memory products for AI, HPC, and data centers.

Qualifications

• Pursuing a Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Knowledge of ASIC design flow concepts: synthesis, place-and-route, STA, and physical verification.
• Experience with programming or scripting languages such as Python, Tcl, Perl, and Shell.
• Strong analytical, problem-solving, communication, and teamwork skills.
• Familiarity with AI-enabled tools and LLMs like Copilot or Claude.

Responsibilities

• Support physical implementation of SoC design blocks: floorplanning, placement, clock tree synthesis, routing, and optimization.
• Analyze timing, power, area, congestion, and physical verification results for improvements.
• Assist with static timing analysis, timing closure, and debugging across modes and process corners.
• Develop and enhance automation tools, scripts, reports, and workflows.
• Collaborate with cross-functional teams to document results and present findings.

Skills

ASIC design flow

Timing analysis

Scripting: Python/Tcl/Perl/Shell

Problem solving

Communication

Teamwork

AI/LLM familiarity

Education

Master's degree in Electrical/Computer Engineering or related field

Tools

Cadence Innovus/Tempus

Synopsys ICC2/PrimeTime

Siemens Calibre

Job description

Micron Technology, Inc. is seeking a SoC Physical Design Intern on the HBM team in the United States.

You will support the implementation of advanced HBM SoC designs and gain hands-on experience in physical design methodologies, timing analysis, signoff flows, and automation. You will work with veterans across architecture, RTL, verification, DFT, and signoff, contributing to next-generation memory products for AI, HPC, and data centers.