HBM IO Design Architect for AI/ML Systems

Micron Technology, Inc; Richardson (TX); On-site; USD 150,000 - 210,000; Full time

Job summary

Micron Technology, Inc. in Richardson, TX, is seeking an HBM IO Design Architecture Engineer to own the end-to-end design quality system for high bandwidth memory products.

You will define quality processes from architecture to silicon, analyze silicon measurements and simulations, and drive AI-driven analytics to accelerate fault isolation and design improvements. This position requires hands-on experience in high-speed IO, clocking design at 32 Gbps+, and cross-functional collaboration across

Qualifications

• Hands-on experience in high-speed IO design and verification.
• Experience with clocking design and parasitic extraction.
• Familiarity with off-chip protocols (UCIe, HBM, DDR, PCIe, MIPI).
• Ability to analyze silicon measurements and simulations along with cross‑functional collaboration.

Responsibilities

• High-speed IO design architecture for HBM products.
• Define and standardize IO design quality process from architecture to silicon.
• Correlate silicon measurements and simulations for circuit level design analysis.
• Contribute to cross-group communication for standardization and success.
• Solicit input from CAD, modeling, and verification groups to ensure design quality.
• Drive innovation into future memory generations with AI‑assisted analytics.

Skills

High-speed IO design

Clocking design 32Gbps+

Circuit verification & optimization

HBM/DDR/PCIe/MIPI knowledge

Documentation & communication

Circuit debugging

Packaging environments (CoWoS, HBM)

Education

MS or PhD in EE

Job description

Micron Technology, Inc. in Richardson, TX, is seeking an HBM IO Design Architecture Engineer to own the end-to-end design quality system for high bandwidth memory products.

You will define quality processes from architecture to silicon, analyze silicon measurements and simulations, and drive AI-driven analytics to accelerate fault isolation and design improvements. This position requires hands-on experience in high-speed IO, clocking design at 32 Gbps+, and cross-functional collaboration across