HBM IO Architecture Lead: High-Speed Analog & Timing

Micron; Richardson (TX); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Medical Insurance

Dental Insurance

Vision Insurance

Paid Time Off

Paid Holidays

Job summary

Micron Technology is seeking an experienced HBM Architecture Engineer to define and drive the architecture of high-speed analog and mixed-signal IO subsystems for HBM products. You will influence architecture choices and mentor teams across design and product engineering to translate concepts into silicon.

The role focuses on PHY IO architecture, timing methodologies, calibration schemes, and silicon learning frameworks to achieve industry-leading bandwidth, power efficiency, and robustness.

Qualifications

• MS or PhD in Electrical Engineering or related field.
• 7+ years of semiconductor design, architecture, or technology development.
• Expertise in analog and mixed-signal IO design and architecture.
• Deep knowledge of high-speed transmitter/receiver, clocking, and timing architectures.

Responsibilities

• Define and drive next-generation HBM PHY and IO architecture balancing perf, power, area, and reliability.
• Architect transmit/receive paths including clocking, signaling, equalization, timing alignment, and interface optimization.
• Define and optimize analog calibration architectures and adaptive tuning methodologies.
• Develop IO timing budgets, design targets, and margins across process/voltage/temperature/packaging.

Skills

HBM IO architecture

Analog/mixed-signal design

High-speed transmitter/receiver

Clocking/timing architectures

Technical communication

Education

MS or PhD in EE or related field

Tools

Circuit modeling

Job description

Micron Technology is seeking an experienced HBM Architecture Engineer to define and drive the architecture of high-speed analog and mixed-signal IO subsystems for HBM products. You will influence architecture choices and mentor teams across design and product engineering to translate concepts into silicon.

The role focuses on PHY IO architecture, timing methodologies, calibration schemes, and silicon learning frameworks to achieve industry-leading bandwidth, power efficiency, and robustness.