HBM Foundry Interface Design Engineer for AI-Driven Memory

Micron Technology, Inc.; Richardson (TX); On-site; USD 146,000 - 297,000; Full time

Job summary

Micron Technology, Inc. seeks a senior engineer for the HBM Design Architecture team within the HBM DRAM Engineering Group.

You will bridge internal design groups, foundries, and technology teams to translate advanced process capabilities into scalable, high-performance memory architectures powering AI workloads. Based onsite in Richardson, TX, you will influence TSV and BEOL considerations, run HSPICE and BEOL analyses, and collaborate on silicon learning, DTCO, PDK enablement and design

Qualifications

• 6+ years in semiconductor industry with advanced CMOS tech development.
• Strong understanding of CMOS nodes, FinFETs, and process integration.
• Hands-on with HSPICE simulations, device characterization and PPA analysis.
• Experience with memory products like DRAM, HBM or SRAM is valued.
• Ability to drive AI-enabled engineering and automation.

Responsibilities

• Foundry interface and technology alignment with design teams.
• Perform circuit simulations and post-layout analysis; optimize BEOL routing.
• Plan test chips, analyze silicon data and correlate to simulations.
• PDK evaluation, design guidelines, and flow enablement with CAD teams.
• Lead AI-enabled productivity initiatives across DTCO and development.

Skills

Semiconductor industry experience

CMOS technology nodes

FinFET devices

Process integration

HSPICE simulations

Device characterization

PPA analysis

Parasitic extraction

Physical verification

Memory products (DRAM/HBM/SRAM)

AI-enabled engineering practices

Silicon learning and qualification

Education

BS, MS, or PhD in Electrical/Computer Engineering

Tools

HSPICE

PDK development and validation

Job description

Micron Technology, Inc. seeks a senior engineer for the HBM Design Architecture team within the HBM DRAM Engineering Group.

You will bridge internal design groups, foundries, and technology teams to translate advanced process capabilities into scalable, high-performance memory architectures powering AI workloads. Based onsite in Richardson, TX, you will influence TSV and BEOL considerations, run HSPICE and BEOL analyses, and collaborate on silicon learning, DTCO, PDK enablement and design