Senior DRAM Design Engineer for HBM AI Workloads

Micron; Garland (TX); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Medical/Dental/Vision plans

Paid time off & holidays

Competitive benefits

Job summary

Micron Technology in Garland, Texas, is seeking a Senior Member of Technical Staff or Member of Technical Staff, DRAM Design Engineer in the next‑generation HBM Architecture team. You will drive architecture optimization for 3D‑stacked memories, collaborating with memory systems experts to deliver high‑bandwidth, energy-efficient solutions for AI workloads.

The role requires strong DRAM design experience, mixed-signal expertise, and a track record of delivering scalable memory architectures.

Qualifications

• 8+ years of proven DRAM-based memory design experience.
• Strong mixed-signal design experience with analog and synthesis flows.
• DRAM circuit design in cell arrays, sense amps, decoders, IO or power distribution.
• Experience with HBM or other stacked memory architectures is preferred.

Responsibilities

• Identify and develop novel DRAM circuit architectures for AI workloads to improve bandwidth and energy efficiency.
• Collaborate to identify bottlenecks and define architectural hypotheses.
• Validate hypotheses through schematic-level design, SPICE simulation, and tradeoff analysis for PPA feasibility.
• Partner with layout designers for floorplanning studies and DFT/DFY optimization.
• Define and maintain design specifications and architecture documentation.

Skills

DRAM design experience

SPICE-based tools

Mixed-signal design

Strong communication

Education

Masters or PhD in EE/CS/CE

Tools

SPICE (FineSim/HSPICE)

Job description

Micron Technology in Garland, Texas, is seeking a Senior Member of Technical Staff or Member of Technical Staff, DRAM Design Engineer in the next‑generation HBM Architecture team. You will drive architecture optimization for 3D‑stacked memories, collaborating with memory systems experts to deliver high‑bandwidth, energy-efficient solutions for AI workloads.

The role requires strong DRAM design experience, mixed-signal expertise, and a track record of delivering scalable memory architectures.