Foundry Interface Design Architect - HBM & AI-Driven

Micron Technology; Richardson (TX); On-site; USD 146,000 - 297,000; Full time

Job summary

Micron Technology is seeking a senior engineer to support the design and development of next-generation HBM DRAM products onsite. You will bridge internal design teams, foundries, and technology development groups, advancing TSV, BEOL, and PDK enablement while improving performance and power efficiency.

Qualifications include 6+ years in semiconductors, hands-on HSPICE and PPA, and knowledge of CMOS node trends. The role emphasizes collaboration across global teams and silicon validation efforts.

Qualifications

• BS/MS/PhD or equivalent experience in Electrical or Computer Engineering or related field.
• 6+ years of semiconductor industry experience and knowledge of advanced CMOS tech.
• Hands-on with HSPICE, device characterization, and PPA analysis.

Responsibilities

• Act as primary interface between foundry partners and Micron design teams.
• Perform HSPICE simulations for technology evaluation and design optimization.
• Plan technology evaluation test chips and analyze post-silicon data.
• Collaborate on PDK evaluation, design guidelines, and flow enablement.
• Identify AI-enabled workflows to boost engineering productivity.

Skills

Semiconductor industry experience

HSPICE simulations

Device characterization

Standard cell benchmarking

PPA analysis

Parasitic extraction

Education

BS/MS/PhD in Electrical or Computer Engineering or related field

Tools

PDK evaluation tools

Job description

Micron Technology is seeking a senior engineer to support the design and development of next-generation HBM DRAM products onsite. You will bridge internal design teams, foundries, and technology development groups, advancing TSV, BEOL, and PDK enablement while improving performance and power efficiency.

Qualifications include 6+ years in semiconductors, hands-on HSPICE and PPA, and knowledge of CMOS node trends. The role emphasizes collaboration across global teams and silicon validation efforts.