Hardware Verification Intern for AI Inference SoC

The Consensus; San Jose (CA); On-site; USD 34,440 - 55,104; Full time

Benefits offered by this job

12-week internship

Housing support

Meals in office

Mentorship program

Job summary

Etched is seeking a Design Verification intern to verify custom IPs powering our chips, including systolic arrays, DMA engines, and NoCs. You will work with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the hardware-software stack.

Fall '26, Spring '27, and Summer '27 internships are offered. We value fast learners with a background in EE/CE, SystemVerilog/UVM or Python, and familiarity with verification work and test benches.

Qualifications

• Pursuing a degree in EE/CE or related field
• Familiarity with high-speed digital logic and verification
• Exposure to ASIC/SoC design concepts
• Familiarity with SystemVerilog, UVM, or Python
• Familiarity with verification work and test benches
• Familiarity with physical design flows and tooling
• Willingness to learn about transformers and modern AI concepts

Responsibilities

• Verify IPs powering our chips to ensure robustness and silicon-readiness
• Collaborate with architects, RTL designers, and SW/FW/emulation teams
• Validate correctness and performance across hardware-software stack
• Contribute to verification efforts for systolic arrays, DMA engines, and NoCs

Skills

SystemVerilog

UVM

Python

Test benches

High-speed digital logic

ASIC/SoC concepts

Hardware verification

Learning quickly about AI transformers

Education

Pursuing Bachelor's, Master's, or PhD in electrical engineering, computer engineering, or related field

Job description

Etched is seeking a Design Verification intern to verify custom IPs powering our chips, including systolic arrays, DMA engines, and NoCs. You will work with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the hardware-software stack.

Fall '26, Spring '27, and Summer '27 internships are offered. We value fast learners with a background in EE/CE, SystemVerilog/UVM or Python, and familiarity with verification work and test benches.