Design Verification Engineer – High-Performance Inference IP

The Consensus; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

Housing subsidy

Relocation support

Wellness benefits

Daily lunch + dinner in office

Unlimited compute budget

Job summary

Etched is seeking a Design Verification Engineer to join our Internal IP DV team in San Jose. You will verify custom IP cores powering our chips, including systolic arrays, DMAs, and NoCs, ensuring robustness, high performance, and silicon readiness.

You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate the full hardware-software stack, build UVM/testbenches, and contribute to DV infrastructure and coverage models.

Qualifications

• Proficiency with UVM and SystemVerilog.
• Strong debugging and problem-solving skills for complex digital designs.
• Solid knowledge of computer architecture and digital design fundamentals.
• Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.

Responsibilities

• Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
• Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
• Debug complex datapath and protocol issues in RTL and testbench environments.
• Work closely with architects and designers to validate functionality and design intent.
• Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.
• Contribute to reusable DV infrastructure, coverage models, and methodology improvements.

Skills

UVM

SystemVerilog

Debugging

Computer architecture

Digital design

Python scripting

Tools

SVA

Formal verification

Python

Job description

Etched is seeking a Design Verification Engineer to join our Internal IP DV team in San Jose. You will verify custom IP cores powering our chips, including systolic arrays, DMAs, and NoCs, ensuring robustness, high performance, and silicon readiness.

You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate the full hardware-software stack, build UVM/testbenches, and contribute to DV infrastructure and coverage models.