DV Intern

The Consensus; San Jose (CA); On-site; USD 34,440 - 55,104; Full time

Benefits offered by this job

12-week internship

Housing support

Meals in office

Mentorship program

Job summary

Etched is seeking a Design Verification intern to verify custom IPs powering our chips, including systolic arrays, DMA engines, and NoCs. You will work with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the hardware-software stack.

Fall '26, Spring '27, and Summer '27 internships are offered. We value fast learners with a background in EE/CE, SystemVerilog/UVM or Python, and familiarity with verification work and test benches.

Qualifications

• Pursuing a degree in EE/CE or related field
• Familiarity with high-speed digital logic and verification
• Exposure to ASIC/SoC design concepts
• Familiarity with SystemVerilog, UVM, or Python
• Familiarity with verification work and test benches
• Familiarity with physical design flows and tooling
• Willingness to learn about transformers and modern AI concepts

Responsibilities

• Verify IPs powering our chips to ensure robustness and silicon-readiness
• Collaborate with architects, RTL designers, and SW/FW/emulation teams
• Validate correctness and performance across hardware-software stack
• Contribute to verification efforts for systolic arrays, DMA engines, and NoCs

Skills

SystemVerilog

UVM

Python

Test benches

High-speed digital logic

ASIC/SoC concepts

Hardware verification

Learning quickly about AI transformers

Education

Pursuing Bachelor's, Master's, or PhD in electrical engineering, computer engineering, or related field

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As aDesign Verification intern, you will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack. We are looking for Fall '26, Spring '27, and Summer '27 interns.

You may be a good fit if you have

• Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.

• Familiarity with high-speed digital logic

• Exposure to ASIC or SoC design concepts

• Familiarity with SystemVerilog, UVM, or Python

• Familiarity with verification work and writing test benches

• Familiarity with physical design flows and tooling

• Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

• Familiarity with modern ML and LLM model architectures

• UVM or formal verification experience

• Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

• 12-week paid internship

• Generous housing support for those relocating

• Daily lunch and dinner in our office

• Based at our office in San Jose, CA

• Direct mentorship from industry leaders and world‑class engineers

• Opportunity to work on one of the most important problems of our time

For any questions, contact [e-mail]

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer‑like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in‑person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.