Frontend Infrastructure CAD Engineer for ASIC/SoC IP (Hybrid)

Ericsson Inc.; Austin (TX); Hybrid; USD 178,000 - 195,000; Full time

Benefits offered by this job

Health benefits

401(k) plan

Stock Purchase Plan

Paid time off

Job summary

Ericsson Inc. seeks a Developer (Front End Infrastructure CAD Engineer) in Austin, TX, offering hybrid work within commuting distance. The role focuses on developing, deploying, and supporting complex EDA tools for ASIC/SoC/FPGA IP design and verification.

The candidate will model, design RTL, verify, synthesize, and physically validate designs, collaborating with tool vendors and foundries. Proficiency in Verilog/SystemVerilog/VHDL/UVM/SystemC and scripting is required.

Qualifications

• Experience with ASIC/SoC/FPGA IP using Verilog/SystemVerilog/VHDL/UVM/SystemC.
• Improve and optimize FE IP design/verification flows for ASIC/SoC/FPGA.
• Partner with EDA tool vendors to troubleshoot and streamline tool integration.
• Scripting and automation using Python, Perl, Bash, csh, tcl.
• Manage compute infrastructure migrations and CI/CD automation with Jenkins.

Responsibilities

• Collaborate with EDA tool vendors and foundries to troubleshoot issues and enhance design processes.
• Perform modeling, RTL design, verification, systemization, integration, synthesis, testing, placement and routing.
• Handle timing, electrical checks, physical checks and hardware validation.
• Develop scripts and automation to improve workflow efficiency and tool integration.

Skills

Verilog

SystemVerilog

VHDL

UVM

SystemC

Python

Perl

Bash

csh

tcl

Jenkins

Linux

Education

Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field

Master's degree in Electrical Engineering, Electronics Engineering, or a related field

Tools

Red Hat Enterprise Linux

SUSE Linux Enterprise Server

Jenkins

Job description

Ericsson Inc. seeks a Developer (Front End Infrastructure CAD Engineer) in Austin, TX, offering hybrid work within commuting distance. The role focuses on developing, deploying, and supporting complex EDA tools for ASIC/SoC/FPGA IP design and verification.

The candidate will model, design RTL, verify, synthesize, and physically validate designs, collaborating with tool vendors and foundries. Proficiency in Verilog/SystemVerilog/VHDL/UVM/SystemC and scripting is required.