Senior ASIC RTL Design Engineer - AI Hardware (Hybrid/Remote)

Cerebras; Sunnyvale (CA); Hybrid; USD 200,000 - 290,000; Full time

Benefits offered by this job

Hybrid work model

Equity

Job summary

Cerebras Systems in Sunnyvale, CA is seeking a Senior Front-End Design Engineer to help design and develop next-generation wafer-scale engine architectures. You will own RTL development, integration with third-party IP, and collaborate with design verification, PD, software, and system teams to deliver high-performance, power-efficient solutions.

Required 8+ years in RTL design, master's degree in CS/EE, and experience with front-end chip integration.

Qualifications

• Master’s degree in CS/EE or equivalent required.
• 8+ years of experience delivering complex RTL designs.
• Experience with front end chip integration and third-party IP.
• Proven track record in high-performance computing and ML-related work.
• Hybrid work environment acceptable.

Responsibilities

• Drive all aspects of chip design from spec to RTL and synthesis.
• Collaborate with PD, design verification, software, and systems teams.
• Debug silicon-level functional, timing, and power issues.
• Ensure designs meet performance, power, and area goals.
• Coordinate with external vendors during development.

Skills

RTL design

Frontend chip integration

High-performance computing

GPU/CPU designs

Networking (TCP/IP RDMA Ethernet)

Python scripting

TCL scripting

Education

Master’s degree in CS/EE or equivalent

Tools

FPGA toolchain

Place and Route

Floor planning

Timing Analysis

ASIC vendor management

Job description

Cerebras Systems in Sunnyvale, CA is seeking a Senior Front-End Design Engineer to help design and develop next-generation wafer-scale engine architectures. You will own RTL development, integration with third-party IP, and collaborate with design verification, PD, software, and system teams to deliver high-performance, power-efficient solutions.

Required 8+ years in RTL design, master's degree in CS/EE, and experience with front-end chip integration.