Senior ASIC Verification Engineer - 5G IP (On-site)

Ericsson GmbH; Austin, Northern (TX, KY); Hybrid; USD 150,000 - 190,000; Full time

Job summary

Ericsson Silicon in Austin, Texas seeks an experienced Design Verification Engineer to lead block-level and IP verification for ASIC IP. You will architect RTL testbenches from scratch, implement SystemVerilog/UVM, and contribute to hardware emulation, software-driven verification, and modeling efforts.

Strong collaboration and mentoring are essential for success. The role requires 10+ years of RTL debugging and a BS/MS in EE/CS or related field, with knowledge in SerDes/PCIe/ARM or Ethernet.

Qualifications

• 10+ years of hands-on RTL debugging at block and/or top level.
• Proven IP/ASIC/SoC/FPGA RTL verification experience.
• Strong SystemVerilog/UVM testbench development.
• Demonstrated ability to architect RTL testbenches from scratch.
• Knowledge of SerDes, PCIe, ARM subsystems, DSPs/accelerators, or Ethernet.
• Proficiency in scripting languages (TCL, Python, Perl).
• Excellent written and verbal communication skills.
• BS/MS in Electrical Engineering, Computer Science, or related field.

Responsibilities

• Lead block-level and top-level ASIC and IP verification efforts.
• Architect and develop comprehensive RTL testbenches from scratch.
• Conduct hands-on verification utilizing SystemVerilog and UVM methodologies.
• Develop behavioral models using TLM (Transaction-Level Modeling).
• Participate in hardware emulation and hardware acceleration verification.
• Drive SW-driven verification initiatives.
• Mentor team members and contribute to technical leadership.
• Participate in defining verification strategies and best practices.

Skills

SystemVerilog/UVM

RTL verification

Scripting: TCL/Python/Perl

Testbench architecture

Hardware verification

Education

BS/MS in Electrical Engineering, Computer Science, or related field

Tools

Emulation platforms

HDL simulators

Job description

Ericsson Silicon in Austin, Texas seeks an experienced Design Verification Engineer to lead block-level and IP verification for ASIC IP. You will architect RTL testbenches from scratch, implement SystemVerilog/UVM, and contribute to hardware emulation, software-driven verification, and modeling efforts.

Strong collaboration and mentoring are essential for success. The role requires 10+ years of RTL debugging and a BS/MS in EE/CS or related field, with knowledge in SerDes/PCIe/ARM or Ethernet.