FPGA Soft CPU Architect – RISC-V/Nios V

Altera; San Jose (CA); On-site; USD 133,000 - 193,000; Full time

Job summary

Altera is seeking an innovative Soft CPU Design Engineer to join its IP Engineering team at the San Jose, CA headquarters. You will design and optimize Soft CPU cores tailored for Altera FPGA architectures, focusing on high performance and area efficiency.

Responsibilities include RTL design in SystemVerilog, PPA optimization, timing closure, configurable ISA extensions, and collaboration with DV teams on simulations and hardware validation.

Qualifications

• Bachelor’s, Master’s, or Ph.D. in Electrical/Computer Engineering or related.
• 3+ years of digital design experience focusing on CPU/Processor RTL and FPGA implementation.
• Proficiency in SystemVerilog or Verilog for FPGA synthesis.
• Knowledge of processor pipelines, hazards, branch prediction, and memory hierarchies.

Responsibilities

• Architect, design, and implement Soft CPU cores mapped to Altera FPGA architectures.
• Optimize PPA for programmable logic around ALMs, M20K/MLAB blocks, DSP columns.
• Drive FPGA synthesis and timing closure using proprietary tool flows.
• Implement configurable features including optional ISA extensions and custom instructions.
• Collaborate with DV teams to create simulations and validate hardware on development boards.

Skills

SystemVerilog

Verilog

Processor RTL design

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree in Electrical/Computer Engineering

Ph.D. in Electrical/Computer Engineering

Tools

Quartus Prime Pro

Platform Designer (Qsys)

TimeQuest Timing Analyzer

Signal Tap

Job description

Altera is seeking an innovative Soft CPU Design Engineer to join its IP Engineering team at the San Jose, CA headquarters. You will design and optimize Soft CPU cores tailored for Altera FPGA architectures, focusing on high performance and area efficiency.

Responsibilities include RTL design in SystemVerilog, PPA optimization, timing closure, configurable ISA extensions, and collaboration with DV teams on simulations and hardware validation.