Principal NoC IP Micro-Architect

Altera; San Jose (CA); On-site; USD 210,000 - 299,000; Full time

Job summary

Altera is seeking a Principal NoC IP Micro-Architect in San Jose, CA to lead end-to-end NoC IP architecture, RTL design, and integration into next‑gen FPGA platforms. You will collaborate across architecture, design, verification, software, physical design, and product teams to deliver high‑performance, power‑efficient interconnects.

This highly visible role requires deep expertise in SoC interconnects, NoC fabrics, RTL development, performance modeling, and system‑level optimization.

Qualifications

• Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related field with 15+ years of related working experience.
• 10+ years of experience in SystemVerilog, VCS/Synopsys simulators, Lint and Synthesis.
• 10+ years of experience in programming with C/C++/Perl/Python/TCL/Unix Shell script.
• 10+ years of experience in FPGA design and programming is a plus.
• 10+ years of experience in RTL validation is a plus.
• 10+ years of experience in development of Network on Chip IPs.
• 5+ years of experience with the usage of AI in development processes for higher efficiency would be a plus.

Responsibilities

• Develops RTL, registers, and high-level design for NoC IPs and related FPGA IPs for full-chip integration.
• Contributes to architecture and microarchitecture feature definitions.
• Creates prototypes, simulations, and system requirements.
• Prepares logic diagrams and codes for system design and test specs.
• Generates device-level bring-up software models and timing/power data.
• Applies RTL implementation to meet power, performance, and area goals with PD collaboration.
• Leads design quality via timing, lint, CDC, RDC, DFT and automation.
• Mentors senior engineers and guides the NOC team through blockers and project challenges.

Skills

SystemVerilog

RTL design

VCS/Synopsys simulators

Lint & Synthesis

C/C++/Perl/Python/TCL/Unix Shell

FPGA design

RTL validation

Network on Chip IPs

AI in development process

Education

Bachelor's or Master's Degree in Electrical/Computer Engineering or related field

Tools

VCS

Synopsys tools

Job description

About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

As a Principal NoC IP Micro-Architect, you will be responsible for the end-to-end architecture, microarchitecture, RTL design, and technical leadership of scalable NoC IP solutions integrated into Altera's next‑generation FPGA platforms. You will work closely with architecture, design, verification, software, physical design, and product teams to deliver high-performance interconnect solutions optimized for power, performance, area (PPA), scalability, and reliability. This is a highly visible technical leadership role requiring deep expertise in SoC interconnect architectures, NoC fabrics, RTL development, performance modeling, and system-level optimization.

Key Responsibilities

• Develops the logic design, register transfer level (RTL) coding, and simulation for Network on Chip IPs and potentially other FPGA IPs & subsystem for integration in full chip designs.
• Participates in the definition of architecture and microarchitecture features of the block being designed.
• Creates prototypes, simulates models, and specifies systems requirements.
• Prepares and designs logic diagrams and codes for implementing system design and test specifications.
• Delivers software models for device level bring up, including user visible functionality, timing, and power.
• Applies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team.
• Strong understanding of the design methodology & advance EDA tools like timing constrains verification, RTL lint, CDC, RDC & DFT to ensure high quality IP development as well as deploying automation & AI to enhanced the development efficiency.
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• As a senior designer of the team, you're also expected to groom next level technical members, technically oversee & guide the entire NOC team as well as proactively anticipate potential design challenges & roadblocks and take mitigation actions to ensure the successful execution of the SS that meets the requirement of the project & schedule.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$209,500 - $299,200 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

Qualifications

• Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related field with 15+ years of related working experience.
• 10 + years of experience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis
• 10+ years of experience in programming with C/C++/Perl/Python/TCL/Unix Shell script
• 10+ years of experience in FPGA design and programming is a plus.
• 10+ years of experience in RTL validation is a plus.
• 10+ years of experience in development of Network on Chip IPs.
• 5+ years of experience with the usage of AI with development process for high efficiency development would be a great plus.

Job Type

Regular

Shift

Shift 1 (United States of America)

Primary Location

San Jose, California, United States

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Altera

Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy‑to‑use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.