Senior FPGA Physical Design Engineer

Altera; San Jose (CA); On-site; USD 119,000 - 169,000; Full time

Job summary

Altera, the world’s largest pure-play FPGA solutions provider, seeks a Physical Design Engineer to join our Silicon Design Automation & Implementation team in San Jose, CA. You will contribute to the implementation of custom IP and SoC designs from RTL through GDSII, supporting timing closure, power optimization, and design signoff for next-generation FPGA products.

You will work closely with architecture, RTL, DFT, synthesis, verification, and methodology teams to deliver manufacturing-ready

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 3+ years in semiconductor Physical Design; RTL through GDSII experience.
• Experience with CTS, floorplanning, S/R, STA, LVS/DRC, and signoff.

Responsibilities

• Perform block-level physical design implementation from RTL through GDSII.
• Support synthesis, floorplanning, place and route, CTS, timing analysis and optimization.
• Contribute to physical verification and signoff activities.
• Analyze design results and implement corrective actions with cross-functional teams.
• Collaborate with RTL, DFT, CAD, Architecture, Verification, and Product Engineering.

Skills

Strong analytical skills

Communication skills

Team collaboration

Problem solving

Education

Bachelors in EE/CE/CS

Tools

Synopsys tools

Cadence tools

Siemens EDA

Job description

Altera, the world’s largest pure-play FPGA solutions provider, seeks a Physical Design Engineer to join our Silicon Design Automation & Implementation team in San Jose, CA. You will contribute to the implementation of custom IP and SoC designs from RTL through GDSII, supporting timing closure, power optimization, and design signoff for next-generation FPGA products.

You will work closely with architecture, RTL, DFT, synthesis, verification, and methodology teams to deliver manufacturing-ready