FPGA/ASIC Methodology Engineer: Drive Design & Validation

Teradyne; Reading (MA); On-site; USD 155,000 - 248,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Retirement savings plan (401k)

Job summary

Teradyne in North Reading, MA seeks an ASIC/FPGA Methodology Engineer to define, develop, and maintain FPGA/ASIC design and verification workflows. Strong background in FPGA/embedded design and Linux-based tooling is essential for this role.

The candidate will optimize design flows for Vivado/Quartus, collaborate with design and verification teams, and contribute to CI/CD implementation using Jenkins, Docker, and Git. Excellent problem-solving and teamwork are required.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of industry experience in FPGA and embedded design.
• Strong understanding of FPGA and embedded design principles.
• Hands-on experience with FPGA development tools (e.g., Vivado, Quartus).
• Familiarity with ASIC design flows and methodologies.
• Proficiency in utilities such as Git, Docker, LSF, Jenkins, Artifactory, and Clearcase.
• Knowledge of CI/CD workflows and automation tools.
• Understanding of digital design verification methodologies (e.g., SystemVerilog, UVM).
• Experience with timing analysis, synthesis, and timing closure for FPGA/ASIC designs.
• Familiarity with system-level integration and validation.
• Strong problem-solving skills and the ability to debug complex hardware/software issues.

Responsibilities

• Develop and maintain methodologies for ASIC/FPGA design, verification, and implementation.
• Collaborate with design and verification teams to ensure seamless integration of workflows and tools.
• Support the development of RTL designs using Verilog and assist in debugging complex hardware issues.
• Optimize design flows for FPGA tools such as Vivado, Quartus, or similar platforms.
• Implement and manage CI/CD pipelines using tools like Jenkins, Docker, and Git to streamline development processes.
• Utilize Linux utilities (e.g., Git, Docker, LSF, Clearcase) to support design and verification workflows.
• Provide technical guidance and training to team members on best practices for FPGA/ASIC methodologies.
• Stay updated on industry trends and emerging technologies to continuously improve design methodologies.

Skills

FPGA design

Embedded design

SystemVerilog/UVM

Verilog

CI/CD pipelines

Troubleshooting hardware

Education

Bachelors or Masters in Electrical/Computer Engineering

Tools

Vivado

Quartus

Jenkins

Docker

Git

LSF

ClearCase

Job description

Teradyne in North Reading, MA seeks an ASIC/FPGA Methodology Engineer to define, develop, and maintain FPGA/ASIC design and verification workflows. Strong background in FPGA/embedded design and Linux-based tooling is essential for this role.

The candidate will optimize design flows for Vivado/Quartus, collaborate with design and verification teams, and contribute to CI/CD implementation using Jenkins, Docker, and Git. Excellent problem-solving and teamwork are required.