Senior ASIC Verification Engineer – SoC & UVM Expert

Teradyne; Reading (MA); Hybrid; USD 123,000 - 197,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Flexible Spending Accounts

Retirement savings plans

Life and disability insurance

Paid vacation & holidays

Tuition assistance

Job summary

Teradyne in North Reading, MA, seeks an experienced ASIC Verification Engineer to join the Reference Model team. You will design verification strategies, develop SystemC and SystemVerilog/UVM environments, and collaborate with design, firmware, software, and validation teams to ensure quality and timely delivery.

Ideal candidates hold a BS in a technical field, 4+ years of ASIC/SoC verification, and strong skills in SystemC, C++, Python, and UVM.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field; Master's preferred.
• 4+ years of ASIC/SoC verification experience.
• Experience with SystemC and C++.
• Object Oriented Programming experience.
• Experience developing verification environments using SystemVerilog and UVM.
• Deep understanding of functional verification methodologies, constrained-random verification, and coverage closure.
• Experience with assertion-based verification and scripting using Python, Perl, or similar languages.
• Knowledge of industry-standard EDA simulation and debug tools.
• Experience verifying complex digital designs, interconnects, memory subsystems, and high-speed interfaces.
• Strong analytical and problem-solving skills; excellent collaboration.

Responsibilities

• Verification planning, testbench architecture, and execution for complex ASIC and SoC designs.
• Develop and maintain SystemC and SystemVerilog/UVM reference models.
• Develop and maintain SystemVerilog/UVM-based verification environments, test cases, and reusable verification components.
• Collaborate closely with design, architecture, firmware, software, and validation teams to ensure comprehensive feature coverage.
• Build and execute verification strategies utilizing simulation, coverage-driven verification, assertions, and formal methodologies.
• Support debug and root-cause analysis of functional issues identified during verification and silicon bring-up activities.
• Partner with cross-functional teams to define verification requirements, milestones, and quality metrics.
• Ensure verification deliverables are completed with high quality, on schedule, and aligned with project objectives.

Skills

SystemC

C++

Object Oriented Programming

Python scripting

Constrained-random verification

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field

Master's degree preferred

Tools

SystemVerilog

UVM

EDA tools

Job description

Teradyne in North Reading, MA, seeks an experienced ASIC Verification Engineer to join the Reference Model team. You will design verification strategies, develop SystemC and SystemVerilog/UVM environments, and collaborate with design, firmware, software, and validation teams to ensure quality and timely delivery.

Ideal candidates hold a BS in a technical field, 4+ years of ASIC/SoC verification, and strong skills in SystemC, C++, Python, and UVM.