Junior FPGA Engineer: High-Speed Digital Design

Teradyne; North Reading (MA); On-site; USD 99,000 - 158,000; Full time

Benefits offered by this job

Health benefits

Retirement plan

Tuition assistance

Paid vacation

Job summary

Teradyne in North Reading, MA is seeking a Junior FPGA Engineer to support design and delivery of high-performance FPGA-based solutions at the heart of our test platforms. You will work with experienced engineers on high-speed interfaces, digital systems, and system-level constraints in a collaborative environment.

This role offers growth at the intersection of FPGA design, board-level hardware, and software integration, with onsite three days per week.

Qualifications

• 2+ years of hands-on FPGA design and development.
• Working knowledge of Verilog/SystemVerilog for design and debugging.
• Exposure to AMD (Xilinx) and/or Intel FPGA toolchains, including synthesis, implementation, and timing closure.
• Understanding of digital design fundamentals and ability to interpret schematics.
• Some exposure to high-speed interfaces such as PCIe, DDR, SerDes, or similar technologies and familiarity with AXI4, USB, I2C, and SPI.
• Basic experience bringing up or debugging FPGA designs on hardware platforms.
• Basic TCL and Python scripting skills and experience with version control systems.
• Strong communication and collaboration skills, with an interest in developing system-level thinking.

Responsibilities

• Support FPGA design implementation and bring-up under the guidance of senior engineers.
• Develop FPGA logic for defined interfaces and subsystems as part of a larger design.
• Collaborate with hardware, software, systems, and design verification teams on system-level solutions.
• Support timing closure, resource optimization, lab bring-up, debugging, and basic root cause analysis using JTAG and lab instrumentation.
• Build and maintain TCL and Python scripts that support design and validation workflows.
• Partner in code reviews, design discussions, and PCB and system design decisions that affect FPGA performance.

Skills

FPGA design

Verilog/SystemVerilog

Python scripting

TCL scripting

JTAG debugging

Team collaboration

SystemVerilog UVM

Tools

Xilinx toolchain

Intel FPGA toolchains

Job description

Teradyne in North Reading, MA is seeking a Junior FPGA Engineer to support design and delivery of high-performance FPGA-based solutions at the heart of our test platforms. You will work with experienced engineers on high-speed interfaces, digital systems, and system-level constraints in a collaborative environment.

This role offers growth at the intersection of FPGA design, board-level hardware, and software integration, with onsite three days per week.