Staff FPGA Engineer - High-Performance SoC Test

Teradyne; Reading (MA); Hybrid; USD 123,000 - 197,000; Full time

Benefits offered by this job

Health and dental benefits

Retirement savings plan

Paid vacation & holidays

Tuition assistance

Job summary

Teradyne's Compute Test Division seeks a Staff FPGA Engineer to design and deliver high-performance FPGA-based solutions at the heart of our test platforms in North Reading, MA. You will lead FPGA developments across interfaces, timing, and system constraints.

You will collaborate with hardware, software, and design verification teams, mentor junior engineers, and drive robust, scalable solutions that improve semiconductor device quality and performance.

Qualifications

• 5+ years FPGA design and development experience.
• Strong Verilog/SystemVerilog skills for design and debugging.
• Experience with PCIe, DDR, SerDes, AXI4, USB, I2C, SPI.
• Proficiency in TCL and Python for automation and tooling.
• Experience with AMD (Xilinx) and/or Intel FPGA toolchains.

Responsibilities

• Lead FPGA solutions from requirements through implementation and bring-up.
• Develop high-performance FPGA logic with complex interfaces and subsystem integration.
• Collaborate with hardware, software, systems, and design verification teams.
• Support timing closure, resource optimization, and lab bring-up.
• Partner on PCB and system design decisions impacting FPGA performance.
• Mentor less experienced engineers and provide technical guidance.

Skills

FPGA design

Verilog/SystemVerilog

High-speed interfaces

TCL & Python scripting

System-level thinking

Tools

Xilinx (AMD) toolchains

Intel FPGA toolchains

Lab debugging tools

JTAG & lab instrumentation

Job description

Teradyne's Compute Test Division seeks a Staff FPGA Engineer to design and deliver high-performance FPGA-based solutions at the heart of our test platforms in North Reading, MA. You will lead FPGA developments across interfaces, timing, and system constraints.

You will collaborate with hardware, software, and design verification teams, mentor junior engineers, and drive robust, scalable solutions that improve semiconductor device quality and performance.