Lead FPGA & ASIC Design Manager, Compute Test

Teradyne; North Reading (MA); On-site; USD 156,000 - 249,000; Full time

Benefits offered by this job

Health benefits

Tuition assistance

Paid vacation

Job summary

Teradyne in North Reading, MA, seeks an ASIC and Logic Design Engineering Manager to lead a 4–6 person FPGA/ASIC team for Compute Test products. You will oversee 2–3 FPGA/digital IP projects, collaborate across disciplines, and ensure timely deliverables in budget.

The role requires RTL coding, strong leadership, and experience with Vivado/Quartus, Cadence, clocking constraints, and high‑volume hardware development. Excellent communication skills are essential.

Qualifications

• BSEE or MSEE with 12+ years in Digital FPGA design and integration.
• 5+ years as FPGA/ASIC project lead.
• Experience coding RTL (Verilog).
• Cadence or similar digital simulation tools experience.
• Experience with static timing analysis tools.
• Experience with PCIe, DDR3/4/5, AXI, Ethernet, SPI, SERDES.
• Experience with AMD or Altera FPGAs and tools (Vivado/Quartus).
• Experience with LINT/CDC and bug-tracking tools (Jira).
• Source control experience (Clearcase, Git, CVS) and CI.
• Familiarity with UVM and project scheduling tools.
• Embedded processors and DSP experience a plus.
• C/C++ a plus.
• Excellent presentation and communication skills.
• 2–3 years first-level engineering management experience a plus.
• Hardware for automated test equipment development a plus.

Responsibilities

• Lead multiple FPGA or digital IP development projects.
• Plan and track project schedule and budget.
• Manage staffing levels including full-time and contract resources.
• Collaborate with other disciplines to satisfy product requirements.
• Contribute to FPGA implementation with RTL code as needed.
• Provide technical support for hardware sustaining issues.
• Set goals and coach a 4–6 person team; manage compensation.
• Represent FPGA team on program reviews and core teams.
• Drive FPGA team process improvements.

Skills

Verilog RTL

FPGA design

Project leadership

C/C++

Education

BSEE or MSEE

Tools

Vivado

Quartus

Jira

Git

ClearCase

Job description

Teradyne in North Reading, MA, seeks an ASIC and Logic Design Engineering Manager to lead a 4–6 person FPGA/ASIC team for Compute Test products. You will oversee 2–3 FPGA/digital IP projects, collaborate across disciplines, and ensure timely deliverables in budget.

The role requires RTL coding, strong leadership, and experience with Vivado/Quartus, Cadence, clocking constraints, and high‑volume hardware development. Excellent communication skills are essential.