FE Engineering

Apple; Cupertino (CA); On-site; USD 149,000 - 195,000; Full time

Job summary

Apple in Cupertino, California is seeking an experienced ASIC Timing Engineer to drive timing closure for high-end mobile SoCs. You will develop timing constraints and coverage analysis, and create scripts for critical path analysis, working across RTL, synthesis, and physical implementation.

The role emphasizes collaboration with multiple teams to resolve timing issues and maintain robust timing methodologies and flows throughout the project lifecycle.

Qualifications

• Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field.
• Experience with digital circuits including combinational and sequential logic.
• Familiarity with RTL (Verilog or VHDL) for debugging timing violations and linking to RTL code.

Responsibilities

• Work on timing closure for ASICs in deep sub-micron processes.
• Develop and enhance timing constraints and coverage analysis for SoC.
• Create and maintain timing verification scripts and checks.
• Collaborate with cross-functional teams on timing issues across RTL, synthesis and physical implementation.

Skills

Digital electronics

FSM design

RTL design (Verilog/VHDL)

C/C++ for automation

Python scripting

Static Timing Analysis (STA)

Education

Master's degree in Electrical & Computer Engineering

Job description

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work on timing closure aspect of ASIC chips in deep sub‑micron process. Responsible for SoC (System-on-Chip) design effort interfacing with all disciplines. Develop and enhance timing constraints for a complex, multi‑clock and multi‑voltage SoC. Develop timing constraint and coverage analysis scripts and checks. Develop and enhance timing related scripts for critical path analysis, and various hard macro interfaces. Develop full chip as well as block level constraints for multiple timing modes. Work on timing closure of I/O interfaces. Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation). Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints. Work on Apple SoC chips in deep sub‑micron technologies targeted for high end mobile applications. Work closely with various cross functional teams on resolving complex timing issues for major building blocks of complex SoCs. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $148,987 - $194,700/yr and your base pay will depend on your skills, qualifications, experience, and location.PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field. Experience and/or education must include: Digital Electronic circuits that include Combinational as well as Sequential logic gates to identify critical timing paths, analyzing setup/hold violations and interpreting timing relationships precisely. Understanding Analog Electronic circuits and real chip timing dependency on analog effects such as voltage drops, temperature effects, parasitic resistance and capacitance, and signal integrity, e.g. crosstalk, noise. Utilizing Computer Systems and Computer Architecture to have awareness of pipeline structure, memory hierarchy, and clock domains help in STA (Static Timing Analysis) modeling by providing a clear view of SoC (System‑On‑Chip) interconnections. Utilizing Finite State Machine design to recognize FSM patterns helps define correct design constraints rules such as multi‑cycle paths or false path exceptions. Using RTL (Register Transfer Level) programming languages such as Verilog or VHDL to debug synthesized netlists and timing violations by correlating them to RTL code. Using computer programming languages such as C/C++ or Python for automating parsing of reports, analyzing slack distributions, and generating or refining constraints.

Preferred Qualifications

N/A