Physical Analysis Engineer

Apple; Cupertino (CA); On-site; USD 150,000 - 225,000; Full time

Benefits offered by this job

Stock programs

Medical & dental coverage

Retirement benefits

Discounted products

Job summary

Apple is seeking an experienced IC Power Integrity engineer in Cupertino. You will design, simulate, and validate SOC PDN with advanced process nodes, performing static and dynamic power analyses to support signoff on the PDN and IR budgets.

Responsibilities include debugging EMIR violations, collaborating with CAD/tech teams, and optimizing workflows with Perl/Tcl/Python scripting to improve efficiency and cycle time.

Qualifications

• Design, simulate, and validate SOC PDN with complex structures.
• Perform static and power analyses to sign off on PDN reliability.
• Debug EMIR violations and propose fixes.
• Analyze low-power techniques like gating to meet budgets.
• Automate engineering workflows with scripting.

Responsibilities

• Collaborate with CAD/technology teams across the chip design cycle.
• Drive signoff closure for tape-out with cross-functional teams.
• Identify PDN weaknesses in chip-package co-analysis.
• Develop or automate multi-step engineering workflows to reduce effort.

Skills

Power analysis

EMIR debugging

Problem solving

Scripting (Perl, Tcl, Python)

Debugging complex PDN issues

Education

Bachelor’s degree in Electrical Engineering or related field

Tools

Ansys RedHawk

Cadence Voltus

Job description

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Debug flow related issues and make enhancements as appropriate. Work with all aspects of ASIC physical design including floor planning, clock and power distribution. Use industry standard tools to perform analyses such as Apache Redhawk, Voltagestorm, ETS, PT-SI. Perform various electrical analyses at the chip level, including but not limited to Static/Dynamic IR, EM, Noise and Signal EM. Work multi-functionally with the CAD/technology teams for flow bring up and validation. Collaborate with the implementation team during the entire chip design cycle to drive signoff closure for tape out. Manage schedules and supporting multi-functional engineering effort. 40 hours/week.

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition.

Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Bachelor’s degree or foreign equivalent in Electrical Engineering, Mechatronic Engineering, or related field.

Experience and/or education includes the following:

• Designing, simulating, and validating large SOC PDN (power grid network) with complex structure in the advance technology process node.
• Performing static and power analysis to signoff on the power grid using tools like Ansys RedHawk, or Cadence Voltus.
• Utilizing problem-solving skills, with the ability to debug complex EMIR violations and propose appropriate and effective design fixes.
• Conducting static and dynamic power analysis, analyzing and verifying low power techniques such as power gating, clock gating, to meet project power/IR budgets.
• Performing chip-package co-analysis to identify PDN weakness, such as that caused by dynamic voltage droop, high impedance paths or insufficient decoupling, and assess impact on critical timing paths.
• Creating or automating complex, multi-step engineering workflows, leading to significant reduction in manual efforts and cycle time, using conventional scripting language such as Perl, Tcl, or Python.
• Utilizing post-silicon correlation, collecting and processing DFT scan patterns out of characterization results, and refining pre-silicon EMIR models and signoff methodologies for future projects.

Preferred Qualifications

N/A