Design for Test Engineer

Socket.dev; Cupertino (CA); On-site; USD 147,000 - 218,000; Full time

Benefits offered by this job

Stock options

Medical & dental coverage

Relocation assistance

Education reimbursement

Job summary

APPLE INC in Cupertino, CA seeks an experienced DFT Engineer to design and implement DFT architectures, write Verilog RTL for DFT logic, and collaborate with design and DV teams on timing, power and verification coverage. You will generate ATPG vectors, debug silicon test vectors, and support test time reduction and silicon diagnosis efforts.

The role emphasizes collaboration across DV and design teams, with a base pay range noted and a comprehensive benefits program.

Qualifications

• Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field and 2 years of experience in the job offered or related occupation.
• Designing and verifying RTL using Verilog hardware description language.
• Knowledge of MBIST, march algorithms and memory fault models.
• Designing Joint Test Action Group (JTAG) architecture and programming DFT control registers for chip testing
• Automating DFT design flows using Python or Perl scripting languages
• Knowledge of STA for timing analysis.
• Running RTL and gate-level simulations using industry-standard tools such as VCS or NCSIM to debug and resolve design issues
• Utilizing Automatic Test Pattern Generation (ATPG) tools for scan pattern generation and fault coverage analysis across various fault models
• Performing silicon failure diagnosis and analysis from Automated Test Equipment (ATE) to improve yield and manufacturing processes
• Applying low-power design techniques to reduce overall chip power consumption

Responsibilities

• Develop and implement DFT architecture and document DFT specifications.
• Implement DFT infrastructure.
• Code Verilog Register Transfer Language (RTL) for DFT logic.
• Collaborate with designers to integrate DFT implementations and run various checks.
• Partner with designers on STA (Static Timing Analysis), physical, power and logical issues.
• Coordinate with DV (Design Verification) team to verify DFT implementations in RTL and Gate level, review verification coverage and implement ECOs (Engineering Change Orders).
• Generate ATPG (Automatic Test Patten Generation) structural test vectors and analyze and improve test coverage.
• Engage with test engineers to debug and bring up test vectors on silicon.
• Support TTR (Test time Reduction) and silicon diagnosis efforts.
• Handle schedules and support multi-functional engineering efforts.

Skills

Verilog RTL

MBIST

JTAG/DFT control

Python/Perl scripting

STA timing analysis

RTL & gate sim

ATPG tools

Silicon failure analysis

Low-power design

Memory fault models

Education

Master’s degree in Computer/Electrical/Electronics Engineering or related field with 2 years experience

Tools

VCS

NCSIM

ATPG tools

Job description

Description

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Develop and implement DFT (Design For Test) architecture and document DFT specifications. Implement DFT infrastructure. Code Verilog Register Transfer Language (RTL) for DFT logic. Collaborate with designers to integrate DFT implementations and run various checks. Partner with designers on STA (Static Timing Analysis), physical, power and logical issues. Coordinate with DV (Design Verification) team to verify DFT implementations in RTL and Gate level, review verification coverage and implement ECOs (Engineering Change Orders). Generate ATPG (Automatic Test Patten Generation) structural test vectors and analyze and improve test coverage. Engage with test engineers to debug and bring up test vectors on silicon. Support TTR (Test time Reduction) and silicon diagnosis efforts. Handle schedules and support multi-functional engineering efforts. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $146,717 - $218,000/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.htmlNote: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

• Develop and implement DFT (Design For Test) architecture and document DFT specifications.
• Implement DFT infrastructure.
• Code Verilog Register Transfer Language (RTL) for DFT logic.
• Collaborate with designers to integrate DFT implementations and run various checks.
• Partner with designers on STA (Static Timing Analysis), physical, power and logical issues.
• Coordinate with DV (Design Verification) team to verify DFT implementations in RTL and Gate level, review verification coverage and implement ECOs (Engineering Change Orders).
• Generate ATPG (Automatic Test Patten Generation) structural test vectors and analyze and improve test coverage.
• Engage with test engineers to debug and bring up test vectors on silicon.
• Support TTR (Test time Reduction) and silicon diagnosis efforts.
• Handle schedules and support multi-functional engineering efforts.

Minimum Qualifications

• Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field and 2 years of experience in the job offered or related occupation.
• Experience and/or education must include: Designing and verifying RTL using Verilog hardware description language.
• Knowledge of MBIST, march algorithms and memory fault models.
• Designing Joint Test Action Group (JTAG) architecture and programming DFT control registers for chip testing
• Automating DFT design flows using Python or Perl scripting languages
• Knowledge of STA for timing analysis.
• Running RTL and gate-level simulations using industry-standard tools such as VCS or NCSIM to debug and resolve design issues
• Utilizing Automatic Test Pattern Generation (ATPG) tools for scan pattern generation and fault coverage analysis across various fault models
• Performing silicon failure diagnosis and analysis from Automated Test Equipment (ATE) to improve yield and manufacturing processes
• Applying low-power design techniques to reduce overall chip power consumption

Preferred Qualifications

N/A