Timing Design Engineer

Apple Inc.; Melbourne (KY); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple Inc. in Kentucky seeks an ASIC STA Engineer responsible for timing sign-off, STA and sign-off flow development, and ownership of IP and block timing constraints from synthesis through to sign-off to ensure timing quality.

You will work with RTL, CAD and Physical teams to close timing, develop new timing constraints and improve flows. The ideal candidate has a BS in a technical discipline with 10+ years of ASIC experience, strong scripting skills (Tcl/Perl), and proven timing closure

Qualifications

• BS degree in technical discipline with minimum 10 years of relevant experience.
• Experience with ASIC timing closure flow and methodology.
• Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, variations and signal integrity issues.
• Hands on experience in timing/SDC constraints generation and management.
• Proficient in scripting languages (Tcl and Perl).
• Familiarity with synthesis, DFT and backend related methodology and tools.
• Strong communication skills are a pre-requisite - you will collaborate with many diverse groups at Apple.
• The ideal candidate will be a self-starter and highly motivated to be successful at Apple.

Responsibilities

• Timing sign-off, STA and sign-off flow development.
• Ownership of IP and block level timing constraints from synthesis to sign-off.
• Work with RTL designer to understand design intent and clock structure, with CAD to develop flow, and with Physical design to close/ sign-off timing.
• Develop ideas to verify timing constraints and improve flows.

Skills

Timing constraints

Primetime STA

Tcl scripting

Perl scripting

Communication skills

Education

BS degree in technical discipline

Tools

Primetime

Job description

Apple is where individual imaginations come together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that encourages the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something - you’ll add something.

Description

As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.

Minimum Qualifications

• BS degree in technical discipline with minimum 10 years of relevant experience.

Preferred Qualifications

• Proven knowledge of the ASIC design timing closure flow and methodology.
• 2+ years of experience in writing ASIC timing constraints and timing closure.
• Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues.
• Hands on experience in timing/SDC constraints generation and management.
• Proficient in scripting languages (Tcl and Perl).
• Familiarity with synthesis, DFT and backend related methodology and tools.
• Strong communication skills are a pre-requisite - you will be collaborating with many diverse groups at Apple.
• The ideal candidate will be a self-starter and highly motivated to be successful at Apple.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.