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Apple Inc. is seeking an experienced ASIC STA Engineer to own timing sign-off and develop STA and sign-off flows across the design—from RTL to physical implementation.
The ideal candidate will have extensive experience with timing constraints, variability, and scripting in Tcl and Perl, and will collaborate with RTL, CAD, and backend teams to ensure robust timing closure.
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As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant
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Apple accepts applications to this posting on an ongoing basis.