Timing & Synthesis Engineer

Apple; San Diego (CA); On-site; USD 139,500 - 258,100; Full time

Benefits offered by this job

Comprehensive medical and dental coverage

Employee stock programs

Educational reimbursement

Job summary

A leading technology company in San Diego is seeking a Timing Engineer to develop Wireless SoCs. In this role, you will collaborate with diverse teams to create and manage timing constraints essential for ASIC design. Candidates should hold a Bachelor's degree and possess at least 3 years of experience in the field. This position offers a competitive salary and comprehensive benefits including stock options and educational reimbursements.

Qualifications

• 3+ years of relevant industry experience.
• Strong knowledge of the ASIC design process.
• Expertise in static timing analysis.

Responsibilities

• Create and review timing constraints throughout the project.
• Execute low-power physical synthesis techniques.
• Collaborate with various teams for project success.

Skills

Timing constraint creation

Logic synthesis execution

Scripting languages (TCL, PERL, Python)

Education

Bachelor's degree

Tools

STA tools

Job description

Summary

Come and join Apple’s growing wireless silicon development team. Our Wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy‑efficient design and new technologies that transform the user experience at the product level. This is driven by a world‑class vertically integrated engineering team spanning RF/Analog, Systems/PHY/MAC, RTL design/integration, Emulation, Verification, DFT, Validation, and FW/SW engineering. We encourage you to apply if you enjoy a fast‑paced and exciting environment, collaborating with people across different functional areas, and thrive during critical times.

Description

As a Timing Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators and multiple processor sub‑systems. There will be the opportunity to work closely with SoC architects and IP developers to develop SoCs that meet power, performance, and area goals for Apple’s products. You will help improve the processes, methods, and tools for designing and implementing these large, complex SoCs. Collaboration with multi‑disciplinary groups will be needed to make sure designs are delivered on time and with the highest quality by incorporating targeted checks at every stage of the design process. In this highly visible role, you will be at the center of the ASIC creation effort, interfacing with all disciplines, with a critical impact in getting leading‑edge products launched to delight millions of customers.

Responsibilities

• Full chip and block‑level timing constraint creation, review and closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).
• Execute low‑power physical synthesis techniques, deploying knowledge of UPF and power intent verification.
• Deploy and enhance methodology and flows related to timing constraint verification and timing closure.
• Generation of consistent block and full chip timing constraints.
• Support digital chip integration work and flows (e.g. CDC).
• Collaborate with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve first‑time Silicon success.
• Generally bridge between the RTL front end and place & route worlds.

Minimum Qualifications

• Bachelor’s degree and 3+ years of relevant industry experience.
• Timing constraint (SDC) creation at partition and chip level.
• Logic synthesis execution (verilog RTL to netlist).

Preferred Qualifications

• Strong knowledge of the entire ASIC design process, from RTL through synthesis, static timing analysis and place & route.
• Expertise in STA tools and flow.
• UPF usage for power and voltage islands.
• Knowledge of timing corners, operating modes, process variation and signal integrity‑related issues.
• Skilled in scripting languages (TCL, PERL, Python), both standalone and within EDA tools.
• Proficient in the closure of end‑to‑end logic equivalence (FV, LEC) with functional ECOs in the mix.
• Familiarity with DFT approaches and constraints.
• Proficient with RTL Verilog/VHDL.
• Familiarity with digital top integration flows/methodology/checks.

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $139,500 and $258,100, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

Apple accepts applications to this posting on an ongoing basis.