Hybrid Principal Packaging Engineer: 2.5D/3D & SiP Expert

Renesas; Austin (TX); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Renesas is hiring a Principal Package Design Engineer in the US, with a hybrid setup at San Jose, CA and Austin, TX. You will lead advanced packaging initiatives for high‑performance semiconductors, drive architecture decisions, and coordinate with design, manufacturing, and supplier teams.

Ideal candidates bring deep packaging expertise, strong CAD and simulation skills, and a track record of delivering from concept through high‑volume production.

Qualifications

• MSc or PhD in Electrical Engineering, Materials Science, Mechanical, Chemical Engineering, or related field.
• 5+ years in advanced semiconductor packaging or related packaging and system integration.
• Strong hands-on knowledge of packaging technologies, materials, assembly, and AI infrastructure/data center power applications.

Responsibilities

• Lead the design, development, and qualification of advanced semiconductor packaging solutions (Flip-chip, 2.5D/3D, SiP, BGA/CSP).
• Define package architecture based on electrical, thermal, mechanical and cost requirements with deep simulation.
• Drive OSAT selection and development for new product introductions (NPI).
• Collaborate with IC design, substrate, board, thermal, reliability, applications, and manufacturing teams.
• Oversee package layout reviews, stack-up, material selection and interconnect strategy.
• Perform simulations for signal integrity, thermal, mechanical stress and DFM.
• Develop assembly flows and qualification plans with OSATs and manufacturers.
• Lead root-cause analysis and corrective actions; mentor engineers and lead packaging initiatives.

Skills

Advanced packaging

Thermal modeling

CAD tools

Reliability testing

Cross-functional

Education

MSc/PhD in Electrical Engineering

Tools

Cadence Allegro

SolidWorks

ANSYS

COMSOL

JMP / Minitab

Job description

Renesas is hiring a Principal Package Design Engineer in the US, with a hybrid setup at San Jose, CA and Austin, TX. You will lead advanced packaging initiatives for high‑performance semiconductors, drive architecture decisions, and coordinate with design, manufacturing, and supplier teams.

Ideal candidates bring deep packaging expertise, strong CAD and simulation skills, and a track record of delivering from concept through high‑volume production.