Director, Front-End RTL Design & SoC Leadership

Kepler Computing; San Jose (CA); On-site; USD 270,000 - 310,000; Full time

Job summary

Kepler Computing seeks a Director of Front-End Design to own pre-silicon RTL design for its advanced products in San Jose. You will lead RTL, IP integration, and post-silicon validation from architecture through tapeout with cross-functional teams.

You will mentor engineers, drive design best practices, and define power/clock strategies while ensuring on-schedule milestones in a fast-paced environment.

Qualifications

• 15+ years of hands-on VLSI front-end RTL design experience with multiple successful SoC/ASIC tapeouts.
• Deep expertise in RTL design and micro-architecture (SystemVerilog/Verilog), with strong PPA optimization skills.
• Strong knowledge of low-power design methods: UPF/CPF, clock and power gating, retention and isolation.
• Hands-on experience with synthesis flows and timing closure.
• Skilled with lint, CDC/RDC and formal verification tools.
• Solid knowledge of DFT methods: scan insertion, ATPG, MBIST and JTAG.
• Strong understanding of SoC-level challenges: clock domain crossings, reset architecture, power domains and memory subsystems.
• Experience with post-silicon validation, debug and production test correlation.
• Strong scripting skills (Python, Perl, Shell, Tcl).
• Excellent leadership and communication skills with a proven ability to lead teams in a fast-paced environment.

Responsibilities

• Own pre-silicon RTL design end to end, from micro-architecture through RTL freeze, synthesis handoff and tapeout signoff.
• Define the design execution strategy: RTL coding guidelines, partitioning, clock and reset architecture, low-power strategy and DFT integration.
• Track design execution metrics and present them at milestone reviews.
• Drive IP integration and ensure IP quality meets integration standards.
• Collaborate with architecture, verification, physical design, DFT and software teams for cross-functional integration.
• Set RTL design best practices, review standards and sign-off infrastructure.
• Lead bring-up planning and post-silicon validation, debug and qualification.
• Build, lead and mentor a team of RTL design and IP engineers.

Skills

RTL design leadership

SystemVerilog

Timing closure

Low-power design

DFT methods

Scripting skills

Team leadership

SoC tapeouts

Education

EE/VLSI degree

Tools

Lint tools

CDC/RDC tools

Formal verification tools

Synthesis tools

Job description

Kepler Computing seeks a Director of Front-End Design to own pre-silicon RTL design for its advanced products in San Jose. You will lead RTL, IP integration, and post-silicon validation from architecture through tapeout with cross-functional teams.

You will mentor engineers, drive design best practices, and define power/clock strategies while ensuring on-schedule milestones in a fast-paced environment.