SoC Implementation Lead: End-to-End Tapeout & Validation

Kepler Computing; San Jose (CA); On-site; USD 250,000 - 310,000; Full time

Job summary

Kepler Computing is seeking a seasoned SoC Chip Lead to own chip implementation from architecture to tapeout and post-silicon validation. You will drive front-end design, verification integration, and physical design coordination with DFT/DFX, packaging, and manufacturing interactions.

Lead a team across architecture, verification, and manufacturing, setting best practices and sign-off processes while mentoring engineers through planning and risk mitigation in a fast-paced environment.

Qualifications

• 15+ years of hands-on SoC front-end design and tapeouts.
• Deep expertise in on-chip interconnect and IO subsystems.
• Strong knowledge of floorplanning, timing convergence, power integrity.
• Experience with lint, CDC/RDC, LEC, synthesis, SDC, and formal verification.
• Solid DFT/DFX methods: ATPG, MBIST and JTAG.
• Proficiency with Python, Perl, Tcl, Shell.
• Excellent leadership and communication skills.

Responsibilities

• Own chip implementation end to end: front-end design, verification integration, physical design coordination, DFT/DFX, packaging and manufacturing interaction.
• Drive design-to-spec execution: lint, CDC, LEC, synthesis, SDC constraints and full design convergence.
• Evaluate and integrate IP, weighing trade-offs across performance, power, area, cost and schedule.
• Work with architecture, verification, DFX, physical design, packaging and manufacturing teams so implementation decisions are physically feasible and on schedule.
• Set and enforce implementation best practices, review standards and sign-off infrastructure.
• Lead and mentor design and implementation engineers. Drive planning, resourcing and risk mitigation.

Skills

SoC design

Tapeouts

Interconnect design

Power management

Physical design

DFT/DFX

EDA tools

Scripting: Python

Education

EE/CE degree

Tools

EDA tools

Job description

Kepler Computing is seeking a seasoned SoC Chip Lead to own chip implementation from architecture to tapeout and post-silicon validation. You will drive front-end design, verification integration, and physical design coordination with DFT/DFX, packaging, and manufacturing interactions.

Lead a team across architecture, verification, and manufacturing, setting best practices and sign-off processes while mentoring engineers through planning and risk mitigation in a fast-paced environment.