Director, Memory Design - AI-Optimized Low-Latency Memory

Kepler Computing; San Jose (CA); On-site; USD 270,000 - 310,000; Full time

Job summary

Kepler is seeking a technically deep Director, Memory Design to own memory controller design for Kepler’s memory products. The role sits where memory architecture, digital logic design and system integration meet, requiring hands-on expertise in memory controller architecture, RTL design, and AI workload optimization.

You will lead end-to-end design efforts from architecture to tapeout, drive PPA optimization, and collaborate with architecture, physical design and post-silicon validation teams.

Qualifications

• 15+ years in memory controller architecture and RTL design
• Expert knowledge of memory controller design: scheduling, ECC, refresh, power management and training
• Strong understanding of industry-standard memory protocols and VLSI trade-offs across latency, bandwidth, power and area
• SystemVerilog, front-end flows (synthesis, CDC, formal verification) and scripting (Python, Perl, Tcl)
• Experience with memory controller performance modeling: simulation, queue-depth analysis and scheduler evaluation
• Deep hands-on timing closure experience on complex, high-frequency digital blocks
• Proven record of leading design teams through at least three full-chip tapeouts in advanced process technologies
• Proven ability to work across teams and deliver complex design blocks with small teams

Responsibilities

• Own memory controller design end to end, from architecture to tapeout, including low-latency memory access paths and high-bandwidth interfaces
• Write and maintain high-quality SystemVerilog RTL. Drive PPA optimization and implementation convergence (lint, CDC/RDC, LEC, synthesis, timing closure)
• Define and review functional and formal verification plans, validate SDC timing constraints, and ensure design quality through rigorous reviews
• Work closely with architecture, physical design and post-silicon validation teams
• Lead the investigation and fixing of complex timing violations and structural design issues during physical implementation
• Define and drive adoption of new design methods that improve power efficiency in high-bandwidth memory interfaces
• Set design best practices, keep technical documentation current, and mentor engineers

Skills

Memory architecture

RTL design

Team leadership

Tapeouts

Education

B.Tech/M.Tech/MS/PhD in Electrical/Computer Engineering

Tools

SystemVerilog

Synthesis

CDC

Formal verification

Python

Perl

Tcl

Job description

Kepler is seeking a technically deep Director, Memory Design to own memory controller design for Kepler’s memory products. The role sits where memory architecture, digital logic design and system integration meet, requiring hands-on expertise in memory controller architecture, RTL design, and AI workload optimization.

You will lead end-to-end design efforts from architecture to tapeout, drive PPA optimization, and collaborate with architecture, physical design and post-silicon validation teams.