Director, Front End Design

Kepler Computing; San Jose (CA); On-site; USD 270,000 - 310,000; Full time

Job summary

Kepler Computing seeks a Director of Front-End Design to own pre-silicon RTL design for its advanced products in San Jose. You will lead RTL, IP integration, and post-silicon validation from architecture through tapeout with cross-functional teams.

You will mentor engineers, drive design best practices, and define power/clock strategies while ensuring on-schedule milestones in a fast-paced environment.

Qualifications

• 15+ years of hands-on VLSI front-end RTL design experience with multiple successful SoC/ASIC tapeouts.
• Deep expertise in RTL design and micro-architecture (SystemVerilog/Verilog), with strong PPA optimization skills.
• Strong knowledge of low-power design methods: UPF/CPF, clock and power gating, retention and isolation.
• Hands-on experience with synthesis flows and timing closure.
• Skilled with lint, CDC/RDC and formal verification tools.
• Solid knowledge of DFT methods: scan insertion, ATPG, MBIST and JTAG.
• Strong understanding of SoC-level challenges: clock domain crossings, reset architecture, power domains and memory subsystems.
• Experience with post-silicon validation, debug and production test correlation.
• Strong scripting skills (Python, Perl, Shell, Tcl).
• Excellent leadership and communication skills with a proven ability to lead teams in a fast-paced environment.

Responsibilities

• Own pre-silicon RTL design end to end, from micro-architecture through RTL freeze, synthesis handoff and tapeout signoff.
• Define the design execution strategy: RTL coding guidelines, partitioning, clock and reset architecture, low-power strategy and DFT integration.
• Track design execution metrics and present them at milestone reviews.
• Drive IP integration and ensure IP quality meets integration standards.
• Collaborate with architecture, verification, physical design, DFT and software teams for cross-functional integration.
• Set RTL design best practices, review standards and sign-off infrastructure.
• Lead bring-up planning and post-silicon validation, debug and qualification.
• Build, lead and mentor a team of RTL design and IP engineers.

Skills

RTL design leadership

SystemVerilog

Timing closure

Low-power design

DFT methods

Scripting skills

Team leadership

SoC tapeouts

Education

EE/VLSI degree

Tools

Lint tools

CDC/RDC tools

Formal verification tools

Synthesis tools

Job description

About The Role

We’re looking for a highly experienced Director, Front-End Design to own pre-silicon RTL design and implementation for Kepler’s products. This high-impact leadership role drives execution across RTL design, IP integration, physical design, verification and packaging from micro-architecture definition through tapeout and post-silicon validation.

Responsibilities

• Own pre-silicon RTL design end to end, from micro-architecture through RTL freeze, synthesis handoff and tapeout signoff.
• Define the design execution strategy: RTL coding guidelines, partitioning, clock and reset architecture, low-power strategy and DFT integration.
• Track design execution metrics (RTL quality, lint/CDC status, synthesis QoR) and present them at milestone reviews.
• Drive IP integration and make sure IP quality meets integration standards.
• Work with architecture, verification, physical design, DFT and software teams for smooth cross-functional integration.
• Set RTL design best practices, review standards and sign-off infrastructure.
• Lead bring-up planning and post-silicon validation, debug and qualification.
• Build, lead and mentor a team of RTL design and IP engineers.

Requirements

• B.Tech/M.Tech/MS/PhD in EE, Electronics, VLSI Design or a related field.
• 15+ years of hands‑on VLSI front-end RTL design experience with multiple successful SoC/ASIC tapeouts.
• Deep expertise in RTL design and micro‑architecture (SystemVerilog/Verilog), with strong PPA optimization skills.
• Strong knowledge of low‑power design methods: UPF/CPF, clock and power gating, retention and isolation.
• Hands‑on experience with synthesis flows and timing closure.
• Skilled with industry‑standard lint, CDC/RDC and formal verification tools.
• Solid knowledge of DFT methods: scan insertion, ATPG, MBIST and JTAG.
• Strong understanding of SoC‑level challenges: clock domain crossings, reset architecture, power domains and memory subsystems.
• Knowledge of industry‑standard on‑chip and memory protocols.
• Experience with post‑silicon validation, debug and production test correlation.
• Strong scripting skills (Python, Perl, Shell, Tcl).
• Excellent leadership and communication skills with a proven ability to lead teams in a fast‑paced environment.

Nice to Have

• Familiarity with AI workloads and their memory demands.
• Background in high‑bandwidth memory subsystem design.
• Exposure to hardware/software co‑design (TLM/SystemC).
• Understanding of how RTL interacts with physical design and PD‑driven RTL optimization.
• Experience with 3D innovations.
• Experience with emulation platforms.
• Familiarity with ML‑assisted design optimization tools.
• Prior startup experience with lean teams and aggressive timelines.

Compensation And Benefits

Actual compensation will be determined based on factors including, but not limited to, relevant experience, skills, qualifications, education, job responsibilities and work location.

Kepler offers a comprehensive benefits package to eligible employees, including medical, dental and vision coverage, retirement benefits, time off and additional Kepler benefits as applicable. Eligibility and benefit offerings may vary based on employment status and work location.

Compensation Range: $270K - $310K

Equal Employment Opportunity

Kepler is an Equal Opportunity Employer. We provide equal employment opportunities to all applicants and employees and do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected under applicable federal, state, or local law.

We believe that different backgrounds, experiences, perspectives and ideas make our team stronger and help our employees, our technology and our community thrive.

Reasonable Accommodation

Kepler is committed to providing reasonable accommodations to qualified individuals with disabilities throughout the application and hiring process. If you need a reasonable accommodation to participate in the application or interview process, please contact us at 408-365-4627 or [e-mail].

Fair Chance Hiring

Kepler will consider qualified applicants with criminal histories in accordance with applicable federal, state, and local laws, including the California Fair Chance Act. Applicants are not required to disclose criminal history before a conditional offer of employment except where otherwise permitted or required by applicable law.

Federal Contractor Notice

Kepler is a federal contractor or subcontractor and is committed to its obligations regarding equal employment opportunity. Kepler does not discriminate against qualified individuals on the basis of disability or protected veteran status and takes steps to employ and advance in employment qualified individuals with disabilities and protected veterans.