Senior Full-Chip Verification Architect (UVM, SV, HVL)

Mirafra Technologies; San Jose (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

Mirafra Technologies in California seeks an Architect to build block and full-chip verification environments using HVLs and constrained-random techniques for SoCs with embedded CPUs and mixed-signal interfaces.

You will develop test plans, write tests in C, SV, and UVM, and debug RTL and gate simulations with design engineers to verify fixes. Diagnostics for FPGA prototype validation and ASIC will be written, silicon bugs reproduced in simulation, and verification scripts automated.

Qualifications

• Develop test plans and coverage metrics from specifications and write block and chip-level tests in C, SV, UVM.
• Debug RTL and gate simulations and work with design engineers to verify fixes.
• Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.
• Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.
• Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.
• Evaluate latest verification methodologies and develop scripts to automate verification.

Responsibilities

• Develop test plans and coverage metrics from specifications and write block and chip-level tests in C, SV, UVM.
• Debug RTL and gate simulations and work with design engineers to verify fixes.
• Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.
• Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.
• Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.
• Evaluate latest verification methodologies and develop scripts to automate verification.

Skills

UVM

SystemVerilog

SVA

Constrained random

Tools

C

Verilog

Job description

Mirafra Technologies in California seeks an Architect to build block and full-chip verification environments using HVLs and constrained-random techniques for SoCs with embedded CPUs and mixed-signal interfaces.

You will develop test plans, write tests in C, SV, and UVM, and debug RTL and gate simulations with design engineers to verify fixes. Diagnostics for FPGA prototype validation and ASIC will be written, silicon bugs reproduced in simulation, and verification scripts automated.