Senior Silicon Verification Engineer (Remote)

MatX; Mountain View (CA); Hybrid; USD 160,000 - 600,000; Full time

Benefits offered by this job

4 weeks PTO

Remote work up to 3 weeks

Health insurance

401K with company match

Professional development budget

Team meals

Commute reimbursement

Mental health benefit

Parental leave

Job summary

MatX in Mountain View, CA is seeking a seasoned silicon verification engineer to contribute to scalable verification across blocks, subsystems, and fullchip tapeouts. You will own verification at subsystem and chip level, create testbenches and tests to achieve coverage closure, and drive reviews for sign-off on milestones.

The role requires 5+ years in silicon verification, end-to-end tapeout experience, and proficiency in SystemVerilog/UVM, ABV, Python, and C/C++.

Qualifications

• 5+ years silicon verification experience
• End-to-end verification from architecture to tapeout
• Proficiency in SystemVerilog/UVM and ABV

Responsibilities

• Contribute to verification methodology across blocks, subsystems, fullchip, and system-level validation
• Own verification at subsystem and chip level; create testbenches, tests, and artifacts for coverage closure
• Plan and drive reviews on verification test plans, execution progress, and closure toward silicon milestones

Skills

Silicon verification

Verification planning

Testbench development

End-to-end tapeout

Tools

SystemVerilog/UVM

ABV

Python

C/C++

Job description

MatX in Mountain View, CA is seeking a seasoned silicon verification engineer to contribute to scalable verification across blocks, subsystems, and fullchip tapeouts. You will own verification at subsystem and chip level, create testbenches and tests to achieve coverage closure, and drive reviews for sign-off on milestones.

The role requires 5+ years in silicon verification, end-to-end tapeout experience, and proficiency in SystemVerilog/UVM, ABV, Python, and C/C++.