Application Specific Integrated Circuit Design Engineer

RG Talent Inc; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

RG Talent Inc is seeking a Verification Engineer to work onsite in Austin, TX or Sunnyvale, CA. The role focuses on defining and implementing IP/SoC verification plans and building verification test benches using UVM.

You will develop functional tests, drive verification closure with metrics, and collaborate across Design, Model, Emulation, and Silicon validation teams to ensure high design quality.

Qualifications

• BS or MS in Electrical/Computer Engineering or Computer Science.
• Experience with Verilog, SystemVerilog based verification and UVM.
• Experience in IP/sub-system and/or SoC verification.
• Experience with EDA tools and scripting (Python, Perl, Shell).
• Architecting and implementing DV infrastructure and completing verification cycle.

Responsibilities

• Define and implement IP/SoC verification plans, build verification test benches.
• Develop functional tests based on verification test plan.
• Drive Design Verification to closure with defined metrics (test, functional, code coverage).
• Resolve functional failures in the design, partnering with the Design team.
• Collaborate with cross-functional teams like Model, Emulation, and Silicon validation.

Skills

UVM

Verilog/SystemVerilog

C/C++ verification

Python

Design verification

Education

B.S./M.S. in EE/CE/CS

Tools

Mercurial

Git

SVN

EDA tools

Scripting (Python, Perl, Shell)

Job description

work onsite in Austin TX or Sunnyvale CA(Onsite)

Coming out of Marvell is a strong match

Main thing is STONG UVM

-Python is a plus

Here is the JD

Responsibilities

• Define and

implement IP/SoC verification plans, build verification test benches to

• Develop functional

tests based on verification test plan

• Drive Design

Verification to closure based on defined verification metrics on test

plan, functional and code coverage

and resolve functional failures in the design, partnering with the Design

team

• Collaborate with

cross-functional teams like Design, Model, Emulation, and Silicon

validation teams towards ensuring the highest design quality

Minimum Qualifications

• B.S or M.S degree

in Electrical Engineering, Computer Engineering or Computer Science

in Verilog, SystemVerilog, C/C++ based verification, and UVM methodology

• Experience in

IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM

based methodologies

• Experience in EDA

tools and scripting (Python, Perl, Shell) used to build tools and flows

for verification environments.

• Experience in

architecting and implementing Design Verification infrastructure and

executing the complete verification cycle

Preferred Qualifications

• Experience in the

development of UVM based verification environments from scratch

• Experience with

Design verification of Data-center applications like Video, AI/ML, and

• Experience with

revision control systems like Mercurial(Hg), Git or SVN