Senior Verification Engineer — SystemVerilog/UVM

Platform Recruitment; San Jose (CA); On-site; USD 100,000 - 130,000; Full time

Job summary

A photonics start-up in California is seeking a verification engineer to enhance their verification infrastructure. The successful candidate will implement testing frameworks, debug issues, and collaborate with design teams. Essential qualifications include deep knowledge of verification methodologies, especially in SystemVerilog and UVM, along with experience in high-speed protocols like PCIe and SERDES. This is an exciting opportunity to work within a leading-edge company making significant advancements in energy efficiency.

Qualifications

• Deep expertise in verification methodologies, specifically SystemVerilog and UVM.
• Experience with high-speed protocols like PCIe and SERDES is a plus.

Responsibilities

• Implement verification infrastructure and test cases with the design team.
• Debug failures and create track issues to resolution.
• Develop and maintain automated regression test infrastructure.

Skills

Industry-standard verification methodologies

SystemVerilog

UVM

Collaboration with design teams

Tools

Automation tools

Debugging tools

Job description

A photonics start-up in California is seeking a verification engineer to enhance their verification infrastructure. The successful candidate will implement testing frameworks, debug issues, and collaborate with design teams. Essential qualifications include deep knowledge of verification methodologies, especially in SystemVerilog and UVM, along with experience in high-speed protocols like PCIe and SERDES. This is an exciting opportunity to work within a leading-edge company making significant advancements in energy efficiency.