Design Verification Engineers

Tachyum; Las Vegas (NV); On-site; USD 100,000 - 140,000; Full time

Benefits offered by this job

Competitive salary

Benefits package

Professional development

International environment

Bleeding edge tech

Collaborative culture

Job summary

Tachyum is seeking talented Verification Engineers to expand our International Design Verification team in Las Vegas. The role focuses on verification environments, testbenches, and regression for complex hardware designs.

You will work on FPGA emulated platforms, use SystemVerilog and UVM, and collaborate with a Linux toolchain. Excellent communication and a drive to innovate in a fast-paced setting are essential.

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Science.
• 4 years of Design Verification experience.
• Strong understanding of DV goals and challenges.
• Able to thrive in a start-up, fast-paced environment.
• Excellent communication skills.
• Strong SystemVerilog and UVM knowledge.
• Ability to identify failure modes when others are complacent.

Responsibilities

• Verify complex test scenarios on FPGA-emulated platforms.
• Develop and maintain verification environments and tests.
• Collaborate with Linux-based toolchains and Git workflows.
• Contribute to regression, coverage, and formal verification.
• Participate in verification for PCIe and DDR protocols.

Skills

SystemVerilog

UVM

Testbench development

C/C++ programming

Debugging

Education

Bachelor’s or Master’s in Electrical or Computer Science

Tools

Jasper

ACL2

Git

Job description

Location

• Las Vegas, NV

Job Field

• Testing & DV

Overview

We are looking for talented Verification Engineers to expand our International Design Verification team.

Qualifications

• Bachelor’s or Master’s in Electrical or Computer Science
• 4 years of Design Verification experience
• Very good understanding of Design Verification goals and challenges
• Ability to adapt to a start-up fast paced dynamic environment
• Excellent communication skills
• Very good knowledge of SystemVerilog and UVM
• Ability to find what can go wrong when everybody else feels safe

Candidate Skills

• Verification environments architecture and implementation
• Verification tools architecture and implementation
• Processors architecture with understanding of execution pipelines
• GPUs or vector processing engines architecture
• Cache hierarchy and MMU architecture
• Cache coherency protocols
• Standard protocols like PCIe and DDR4/5
• Regression infrastructure architecture and implementation
• Verification process and test plan development
• Assertion-based verification using SVA/OVA
• Functional coverage methodology and implementation
• Formal equivalence checking tools like Jasper
• Theorem provers like ACL2

Experience

• Debugging complex test scenarios
• Working on FPGA emulated platforms
• Working in a Linux environment
• Using git version control system
• Using a scripting language (Perl or Python)
• Using C programming language
• Using C++ programming language
• Using TCL and Expect

Benefits

• Competitive salary and benefits package.
• Opportunities for professional development and advancement.
• International environment and further career progression.
• Getting in touch with bleeding edge technology.
• Collaborative and supportive work environment.