Design Verification Engineer

Apple; Los Angeles (CA); On-site; USD 120,300 - 181,200; Full time

Benefits offered by this job

Comprehensive medical and dental coverage

Employee stock programs

Tuition reimbursement for education

Job summary

A leading technology company in California is seeking a motivated design verification engineer to enhance their silicon development processes. This role focuses on creating comprehensive verification methodologies, with a strong emphasis on SystemVerilog and UVM, ensuring the development of efficient test environments. Ideal candidates will possess solid backgrounds in verification methods and have experience with both serial and parallel protocols. Competitive salary, stock options, and extensive benefits included.

Qualifications

• Deep experience in SystemVerilog and UVM methodologies.
• Background in creating scalable test-benches and verification plans.
• Experience in using simulators and waveform viewers.

Responsibilities

• Study design specifications and create comprehensive test plans.
• Develop infrastructure in SystemVerilog/UVM to stress the design.
• Debug failures from regressions and improve test outcomes.

Skills

Deep knowledge of SystemVerilog

Knowledge in developing scalable and portable test-benches

Experience with verification methodologies and tools

Proficient in automation and coverage collection

Familiarity with C/C++

Experience with serial protocols such as PCIe or USB

Knowledge of scripting languages such as Python

Job description

Overview

Summary At Apple, we work to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. This role is for a digital-focused DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Description In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Furthermore, you will learn to develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage.

Responsibilities

• Study design specification and create test plan
• Develop infrastructure in SystemVerilog/UVM to stress the design
• Develop and fix failures from regressions, close bugs
• Use LLMs to do verification efficiently

Preferred Qualifications

• Deep knowledge of SystemVerilog and UVM
• Deep knowledge in developing scalable and portable test-benches
• Proven experience with verification methodologies and tools such as simulators, waveform viewers
• Build and run automation, coverage collection, gate level simulations
• Some UVM knowledge, C/C++ level knowledge
• Deep experience with serial protocols such as PCIe or USB, parallel protocol such as DDR
• Basic knowledge of formal verification methodology
• Some experience with power-aware (UPF) or similar verification methodology
• Knowledge of one of the scripting languages such as Python, Perl, TCL

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $120,300 and $181,200, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

Apple accepts applications to this posting on an ongoing basis.