Design Verification Engineer - First-Silicon Innovator

Apple Inc.; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

Apple Inc. is seeking an outstandingly hardworking design verification engineer to enable first silicon delivery for IP designs. You will create SV/UVM based testbenches, develop DV methodologies, and drive coverage and sign-off.

In this role you will implement verification plans, bring up DV environments, debug regressions, and measure progress with metrics. LLMs and advanced automation will be used to improve efficiency and quality in pre-silicon verification.

Qualifications

• BS degree required in a technical field and 10+ years of experience.
• Expertise in SystemVerilog/UVM and OOP-based testbench design.
• Strong knowledge of verification methodologies, tools, and metrics.

Responsibilities

• Study design specs and develop test plans and SV/UVM-based testbenches.
• Develop and maintain DV infrastructure and testbenches for IP and IP blocks.
• Debug, fix failures from regressions, and drive coverage goals.
• Apply LLMs to improve verification efficiency and quality.

Skills

OOP concepts

SystemVerilog

UVM

Verification methodologies

Python

Perl

TCL

LLMs for verification

Power-aware verification (UPF)

Digital design knowledge

Education

BS degree in Electrical Engineering / Computer Science / related field

Tools

SystemVerilog tooling

Waveform viewers

Simulators

Automation scripts

UPF tooling

Formal verification tooling

Emulation tools

PCIe

USB

Job description

Apple Inc. is seeking an outstandingly hardworking design verification engineer to enable first silicon delivery for IP designs. You will create SV/UVM based testbenches, develop DV methodologies, and drive coverage and sign-off.

In this role you will implement verification plans, bring up DV environments, debug regressions, and measure progress with metrics. LLMs and advanced automation will be used to improve efficiency and quality in pre-silicon verification.