Digital IC Design Engineer — RTL & Tapeout

Sandia National Laboratories; Albuquerque (NM); On-site; USD 102,000 - 200,000; Full time

Job summary

Sandia National Laboratories is seeking a highly motivated Digital IC Design Engineer to join a collaborative team delivering advanced ASIC solutions for mission and laboratory customers. You will translate system needs into robust RTL through tapeout, coordinating across analog, MEMS, photonics, and physical-design partners.

On any given day, you may review schedules, develop block-level specs, implement RTL and IP, and drive verification, synthesis, and timing closure while collaborating with

Qualifications

• Strong proficiency in RTL design using Verilog/SystemVerilog and synthesizable coding practices.
• Experience with digital design fundamentals: pipelining, clock-domain crossing, FSMs, datapath/control partitioning, timing closure.
• Familiarity with SoC integration, bus protocols (AXI/AHB/APB), and IP block design.
• Ability to use EDA toolflows for synthesis, STA, linting, CDC/RDC checks, and formal verification.
• Solid understanding of CMOS device physics, digital logic, noise margins, and scaling effects.
• Hands-on experience with simulation/verification using UVM or similar.
• Read and interpret schematics, timing diagrams, and SDC constraints.
• Collaborate with analog/physical design/firmware/systems teams for chip integration.

Responsibilities

• Review project schedules and milestones, identify blockers, and drive closure.
• Translate mission needs into block-level specifications and maintain traceability.
• Develop and maintain RTL, integrate IP, and implement CDC/reset strategies and low-power techniques.
• Build and extend verification environments; run regressions and analyze failures.
• Coordinate synthesis and implementation handoff; review timing and power reports.
• Collaborate with analog/MEMS/photonics teams on mixed-signal interfaces.
• Apply 2.5D/3D integration considerations to architecture and implementation tradeoffs.
• Define scan/BIST strategy, test hooks, and observability for lab bring-up.
• Maintain design documentation and present decisions at peer reviews.
• Contribute to R&D in advanced signal/data processing through simulation and test chips.

Skills

RTL design

Verilog/SystemVerilog

Pipelining

Clock-domain crossing

FSMs

Datapath/control

Timing closure

EDA toolflows

Synthesis

STA

CDC/RDC checks

Formal verification

IP integration

AXI/AHB/APB

Low power design

Power gating

Radiation hardened design

Schematic reading

Timing diagrams

SCDC constraints

Collaboration across teams

Tape-out coordination

Education

Bachelor's degree

Tools

EDA tools

Job description

Sandia National Laboratories is seeking a highly motivated Digital IC Design Engineer to join a collaborative team delivering advanced ASIC solutions for mission and laboratory customers. You will translate system needs into robust RTL through tapeout, coordinating across analog, MEMS, photonics, and physical-design partners.

On any given day, you may review schedules, develop block-level specs, implement RTL and IP, and drive verification, synthesis, and timing closure while collaborating with