Silicon Design Engineer: RTL to Tapeout Expert

AMD; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

AMD is seeking a highly motivated Silicon Design Engineer to lead and contribute to design, integration, verification, and characterization of advanced silicon testchips supporting FPGA and ASIC products on leading-edge process technologies.

The candidate should have hands-on RTL-to-GDS implementation experience, strong verification skills, and a track record of successful tapeouts in FinFET/GAA nodes, with scripting proficiency for automation.

Qualifications

• Hands-on silicon design with RTL-to-GDSII experience.
• Strong background in timing, power, and reliability analysis.
• Experience delivering silicon in FinFET 7nm/5nm/3nm or GAA nodes.
• Proficiency with design tools and flow automation (Python/Tcl).

Responsibilities

• Lead end-to-end digital ASIC/SoC physical design from RTL to tapeout.
• Perform floorplanning, CTS, placement, routing, and timing closure.
• Conduct STA/GS tests with PrimeTime; ensure DRC/LVS compliance.
• Develop verification plans and testbenches for post-silicon validation.
• Collaborate with RTL, DFT, package and foundry teams; drive issues to closure.
• Support post-silicon bring-up and lab validation activities.

Skills

Timing analysis

Physical design

RTL-to-GDSII

Synthesis

STA (PrimeTime)

GDSII tapeout

Floorplanning

CTS

Power integrity

Python, Tcl, shell

Education

MS or PhD in EE or related

Tools

Cadence Genus/Innovus

Synopsys Fusion Compiler

Proven verification flows

Job description

AMD is seeking a highly motivated Silicon Design Engineer to lead and contribute to design, integration, verification, and characterization of advanced silicon testchips supporting FPGA and ASIC products on leading-edge process technologies.

The candidate should have hands-on RTL-to-GDS implementation experience, strong verification skills, and a track record of successful tapeouts in FinFET/GAA nodes, with scripting proficiency for automation.