Senior Digital IC Design Engineer – RTL/ASIC

Sandia National Laboratories; New Mexico; On-site; USD 118,000 - 236,000; Full time

Benefits offered by this job

Flexible work arrangements

Relocation assistance

Generous vacation

Job summary

Sandia National Laboratories in New Mexico is seeking a highly skilled Digital IC Design Engineer to deliver advanced ASIC solutions for mission and laboratory customers. You will translate system needs into robust RTL, collaborate across analog, physical design, and firmware teams, and drive tapeout readiness.

You will develop and maintain RTL, integrate IP, and implement low-power and radiation-tolerant designs, while coordinating with PD/MA teams to meet schedule and quality goals.

Qualifications

• Bachelor's degree in a relevant discipline plus at least five years of directly related experience.
• Ability to obtain and maintain a DOE Q clearance.
• Strong proficiency in RTL design using Verilog/SystemVerilog.
• Experience with bus protocols AXI/AHB/APB and IP block design.

Responsibilities

• Translate system needs into block-level specifications (performance, power, area, radiation tolerance, interfaces, testability).
• Develop and maintain RTL, integrate IP, and implement clean CDC/reset strategies and suitable low-power techniques.
• Build verification environments, run regressions, analyze failures, close coverage, and perform lint/CDC/formal checks.
• Coordinate synthesis and implementation handoff; review timing/power reports and debug critical paths.
• Collaborate with analog/physical design teams on mixed-signal interfaces and validate against system models.
• Define scan/BIST strategy and support post-silicon debug planning and test-vector development.

Skills

RTL design

Pipelining

Clock-domain crossing

Timing closure

EDA tools

UVM

SoC integration

AXI bus

IP design

Power aware design

Low power

Radiation hardened design

Schematic reading

Collaboration

Noise margins

3D integration

Education

Bachelor's degree in a relevant discipline

Tools

Synthesis tools

Static Timing Analysis (STA)

UVM verification

Job description

Sandia National Laboratories in New Mexico is seeking a highly skilled Digital IC Design Engineer to deliver advanced ASIC solutions for mission and laboratory customers. You will translate system needs into robust RTL, collaborate across analog, physical design, and firmware teams, and drive tapeout readiness.

You will develop and maintain RTL, integrate IP, and implement low-power and radiation-tolerant designs, while coordinating with PD/MA teams to meet schedule and quality goals.