Digital Design Engineer - ASIC Tapeout & Optimization

Anysilicon

Pasadena (CA)

Presencial

USD 110.000 - 190.000

Jornada completa

hace 17 horas
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Descripción de la vacante

Forza Silicon in Pasadena, CA, is seeking a Digital Design Engineer to lead ASIC design from specification through tapeout, ensuring targets for performance, power, and area. You will collaborate with front-end, verification, and layout teams and drive RTL-to-gate transformations with thorough timing and power analyses.

A strong scripting background is essential for automation. The role requires coordinating design reviews, maintaining documentation, and ensuring adherence to manufacturing

Formación

  • Bachelor's or master's degree in Electrical/Computer Engineering or related field.
  • Proficiency in scripting languages (Perl, Python, Tcl) for automation.
  • Understanding of semiconductor manufacturing processes and design methodologies.
  • Strong knowledge of digital design principles (RTL design and verification).

Responsabilidades

  • Oversee all phases of ASIC design projects from specification to tapeout.
  • Perform floorplanning, placement, routing, and optimization for efficient chip layout.
  • Convert RTL to gate-level netlist and meet area/power/performance targets.
  • Conduct static timing analysis (STA) to meet timing requirements.
  • Perform power analysis and optimization to achieve stringent power targets.
  • Ensure design adheres to manufacturing rules (DRC/LVS).
  • Prepare design for tapeout with final checks and documentation.
  • Collaborate with front-end, verification teams, and EDA tool vendors.
  • Develop and maintain automation scripts to improve design efficiency.
  • Troubleshoot physical design, timing, and power issues.
  • Document design processes and methodologies in detail.
  • Participate in technical reviews with design teams and customers.

Conocimientos

RTL design
Digital design
Scripting
STA & timing

Educación

Bachelor's or Master's in EE/CE

Herramientas

EDA tools

Descripción del empleo

Forza Silicon in Pasadena, CA, is seeking a Digital Design Engineer to lead ASIC design from specification through tapeout, ensuring targets for performance, power, and area. You will collaborate with front-end, verification, and layout teams and drive RTL-to-gate transformations with thorough timing and power analyses.

A strong scripting background is essential for automation. The role requires coordinating design reviews, maintaining documentation, and ensuring adherence to manufacturing

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