Low-Power ASIC Design Engineer for SoC & IP

Anysilicon; Sunnyvale (CA); Hybride; USD 140 000 - 210 000; Plein temps

Résumé du poste

Meta in Sunnyvale, CA seeks skilled Design Engineers to develop advanced hardware accelerators and ASIC IPs for ML, graphics, display, and network acceleration. You will work with top researchers to build low-power solutions and collaborate across DV, PD, and architecture teams.

The role emphasizes micro-architecture, RTL coding, and verification for complex IPs, with hands-on collaboration for design targets related to performance and power optimization.

Qualifications

• Experience in digital design microarchitecture and RTL coding.
• Ability to map algorithms to hardware and specify IP/sub-system integration.
• Strong communication and collaboration skills.

Responsabilités

• Develop micro-architecture, RTL coding, and design verification for complex IPs.
• Collaborate with architects to map algorithms onto hardware and specify integration requirements.
• Assist in performance and power analysis to meet targets.
• Coordinate with Verification, Physical Design, and Design-for-Test teams.
• Drive IP/sub-system micro-architecture and RTL design with DV/PD leads.

Connaissances

Digital design

RTL coding

SoC integration

Microarchitecture

Outils

Synthesis

Timing Closure

Formal Verification

Description du poste

Meta in Sunnyvale, CA seeks skilled Design Engineers to develop advanced hardware accelerators and ASIC IPs for ML, graphics, display, and network acceleration. You will work with top researchers to build low-power solutions and collaborate across DV, PD, and architecture teams.

The role emphasizes micro-architecture, RTL coding, and verification for complex IPs, with hands-on collaboration for design targets related to performance and power optimization.