Design Verification Engineer, SOC & Hardware, Stock Options

Apple Inc.; Santa Clara, Northern (CA, KY); Hybrid; USD 150,000 - 278,000; Full time

Job summary

Apple Inc. is seeking a Design Verification Engineer in Santa Clara, CA to verify the functionality and performance of Apple’s premier SOCs.

You will own test plans, coverage, and testbenches, collaborating with design, micro-architecture, and software teams to ensure high quality designs. Minimum qualifications include a BS with 3+ years of experience and strong SystemVerilog/UVM expertise, plus Python/C/C++ and scripting skills.

Qualifications

• Minimum of BS + 3 years relevant industry experience.
• Strong knowledge of SystemVerilog and digital verification methodologies.
• Experience with constrained random verification, functional/Code coverage, and UVM.
• Proficiency in debugging, architecture review, and testbenches.
• SW programming skills with knowledge of data structures and algorithms.
• Experience with Python, Perl or similar scripting languages.
• Ability to work independently to deliver project goals.
• Excellent interpersonal skills and collaboration across teams.

Responsibilities

• Verify functionality and performance of Apple SOCs.
• Develop test plans, tests and coverage plans and testbenches.
• Review design/architecture specs and collaborate with design, micro-architecture and software teams.
• Define verification methodology and create use-case driven tests and corner cases.
• Communicate and coordinate with multiple teams to ensure quality and coverage.

Skills

Digital verification concepts

SystemVerilog

Python

C/C++

UVM

Computer architecture

Debugging

Constrained random verification

Code coverage

Functional coverage

Education

BS degree in a related field

Tools

Verilog/SystemVerilog tools

Python scripting

Perl scripting

Job description

Apple Inc. is seeking a Design Verification Engineer in Santa Clara, CA to verify the functionality and performance of Apple’s premier SOCs.

You will own test plans, coverage, and testbenches, collaborating with design, micro-architecture, and software teams to ensure high quality designs. Minimum qualifications include a BS with 3+ years of experience and strong SystemVerilog/UVM expertise, plus Python/C/C++ and scripting skills.